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january 2000 1 ? 2000 actel corporation v3.0 hirel fpgas features ? highly predictable performance with 100% automatic placement and routing ? device sizes from 1,200 to 20,000 gates ? up to 6 fast, low-skew clock networks ? up to 202 user-programmable i/o pins ? more than 500 macro functions ? up to 1,276 dedicated flip-flops ? i/o drive to 10 ma ? devices available to dscc smd ? cqfp and cpga packaging ? nonvolatile, user programmable ? logic fully tested prior to shipment ? 100% military temperature tested (C55c to +125c) ? qml certified devices ? proven reliability data available ? successful military/avionics supplier for over 10 years act 3 features ? highest-performance, highest-capacity fpga family ? system performance to 60 mhz over military temperature ? low-power 0.8 cmos technology 3200dx features ? 100 mhz system logic integration ? highest speed fpga sram, up to 2.5 kbits configurable dual-port sram ? fast wide-decode circuitry ? low-power 0.6 cmos technology 1200xl features ? pin for pin compatible with act 2 ? system performance to 50 mhz over military temperature ? low-power 0.6 cmos technology act 2 features ? best-value, high-capacity fpga family ? system performance to 40 mhz over military temperature ? low-power 1.0 cmos technology act 1 features ? lowest-cost fpga family ? system performance to 20 mhz over military temperature ? low-power 1.0 cmos technology product family profile (more devices on page 2 ) family 3200dx act 3 1200xl device A32100DX a32200dx a1425a a1460a a14100a a1280xl capacity system gates logic gates sram bits 15,000 10,000 2,048 30,000 20,000 2,560 3,750 2,500 na 9,000 6,000 na 15,000 10,000 na 12,000 8,000 logic modules s-modules c-modules decode 1,362 700 662 20 2,414 1,230 1,184 24 310 160 150 na 848 432 416 na 1,377 697 680 na 1,232 624 608 na flip-flops (maximum) 738 1,276 435 976 1,493 998 user i/os (maximum) 152 202 100 168 228 140 performance system speed (maximum) 55 mhz 55 mhz 60 mhz 60 mhz 60 mhz 50 mhz packages (by pin count) cpga cqfp 84 208, 256 133 132 207 196 257 256 176 172
2 high-reliability, low-risk solution actel builds the most reliable field programmable gate arrays (fpgas) in the industry, with overall antifuse reliability ratings of less than 10 failures-in-time (fits), corresponding to a useful life of more than 40 years. actel fpgas have been production proven, with more than five million devices shipped and more than one trillion antifuses manufactured. actel devices are fully tested prior to shipment, with an outgoing defect level of less than 100 ppm. (further reliability data is available in the actel device reliability report , at http://www.actel.com/hirel ). benefits minimized cost risk with actels line of development tools, designers can produce as many chips as they choose for just the cost of the device itself. there will be no nre charges to cut into the development budget each time a new design is tried. minimized time risk after the design is entered, placement and routing is automatic, and programming the device takes only about 5 to 15 minutes for an average design. designers save time in the design entry process by using tools with which they are familiar. minimized reliability risk the plice antifuse is a one-time programmable, nonvolatile connection. since actel devices are permanently programmed, no downloading from eprom or sram storage is required. inadvertent erasure is impossible, and there is no need to reload the program after power disruptions. fabrication using a low-power cmos process means cooler junction temperatures. actels non-pld architecture delivers lower dynamic operating current. our reliability tests show a very low failure rate of 6.6 fits at 90c junction temperature with no degradation in ac performance. special stress testing at wafer test eliminates infant mortalities prior to packaging. minimized security risk reverse engineering of programmed actel devices from optical or electrical data is extremely difficult. programmed antifuses cannot be identified from a photograph or by using an sem. the antifuse map cannot be deciphered either electrically or by microprobing. each device has a silicon signature that identifies its origins, down to the wafer lot and fabrication facility. minimized testing risk unprogrammed actel parts are extensively tested at the factory. routing tracks, logic modules, and programming, debug and test circuits are 100 percent tested before shipment. ac performance is ensured by special speed path tests, and programming circuitry is verified on test antifuses. during the programming process, an algorithm is run to ensure that all antifuses are correctly programmed. in addition, actels silicon explorer diagnostic tool uses actionprobe circuitry, allowing 100 percent observability of all internal nodes to check and debug the design. actel fpga description the actel families of fpgas offer a variety of packages, speed/performance characteristics, and processing levels for use in all high reliability and military applications. devices are implemented in a silicon gate, two-level metal cmos process, utilizing actels plice antifuse technology. this product family profile family act 2 act 1 device a1240a a1280a a1010b a1020b capacity system gates logic gates sram bits 6,000 4,000 na 12,000 8,000 na 1,800 1,200 na 3,000 2,000 na logic modules s-modules c-modules decode 684 348 336 na 1,232 624 608 na 295 295 na 547 547 na flip-flops (maximum) 568 998 147 273 user i/os (maximum) 104 140 57 69 packages (by pin count) cpga cqfp 132 176 172 84 84 84 performance system speed (maximum) 40 mhz 40 mhz 20 mhz 20 mhz
3 hirel fpgas unique architecture offers gate array flexibility, high performance, and quick turnaround through user programming. device utilization is typically 95 percent of available logic modules. all actel devices include on-chip clock drivers and a hard-wired distribution network. user-definable i/os are capable of driving at both ttl and cmos drive levels. available packages for the military are the ceramic quad flat pack (cqfp) and the ceramic pin grid array (cpga). see the product plan section on page 6 for details. qml certification actel has achieved full qml certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with mil-prf-38535, the performance specification used by the department of defense for monolithic integrated circuits. qml certification is a good example of actel's commitment to supplying the highest quality products for all types of high-reliability, military and space applications. many suppliers of microelectronics components have implemented qml as their primary worldwide business system. appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for a quality, reliable and cost-effective logistics support throughout qml products life cycles. development tool support the hirel devices are fully supported by actels line of fpga development tools, including the actel desktop series and designer advantage tools. the actel desktop series is an integrated design environment for pcs that includes design entry, simulation, synthesis, and place and route tools. designer advantage is actels suite of fpga development point tools for pcs and workstations that includes the actgen macro builder, designer with directtime timing driven place and route and analysis tools, and device programming software. in addition, the hirel devices contain actionprobe circuitry that provides built-in access to every node in a design, enabling 100 percent real-time observation and analysis of a devices internal logic nodes without design iteration. the probe circuitry is accessed by silicon explorer, an easy to use integrated verification and logic analysis tool that can sample data at 100 mhz (asynchronous) or 66 mhz (synchronous). silicon explorer attaches to a pcs standard com port, turning the pc into a fully functional 18 channel logic analyzer. silicon explorer allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. act 3 description the act 3 family is the third-generation actel fpga family. this family offers the highest-performance and highest-capacity devices, ranging from 2,500 to 10,000 gates, with system performance up to 60 mhz over the military temperature range. the devices have four clock distribution networks, including dedicated array and i/o clocks. in addition, the act 3 family offers the highest i/o-to-gate ratio available. act 3 devices are manufactured using 0.8 cmos technology. 1200xl/3200dx description 3200dx and 1200xl fpgas were designed to integrate system logic which is typically implemented in multiple cplds, pals, and fpgas. these devices provide the features and performance required for todays complex, high-speed digital logic systems. the 3200dx family offers the industrys fastest dual-port sram for implementing fast fifos, lifos, and temporary data storage. act 2 description the act 2 family is the second-generation actel fpga family. this family offers the best-value, high-capacity devices, ranging from 4,000 to 8,000 gates, with system performance up to 40 mhz over the military temperature range. the devices have two routed array clock distribution networks. act 2 devices are manufactured using 1.0 cmos technology. act 1 description the act 1 family is the first actel fpga family and the first antifuse-based fpga. this family offers the lowest-cost logic integration, with devices ranging from 1,200 to 2,000 gates, with system performance up to 20 mhz over the military temperature range. the devices have one routed array clock distribution network. act 1 devices are manufactured using 1.0 cmos technology.
4 military device ordering information application (temperature range) c= commercial (0 to +70c) m = military (C55 to +125c) b = mil-std-883 class b e = extended flow (space level) package type cq = ceramic quad flat pack (cqfp) pg = ceramic pin grid array (cpga) speed grade std = standard speed C1 = approximately 15% faster than standard part number a1010 = 1,200 gatesact 1 a1020 = 2,000 gatesact 1 a1240 = 4,000 gatesact 2 a1280 = 8,000 gatesact 2/1200xl a1425 = 2,500 gatesact 3 a1460 = 6,000 gatesact 3 a14100 = 10,000 gatesact 3 a32100 = 10,000 gates3200dx a32200 = 20,000 gates3200dx device revision package lead count a14100 cq 256 b 1 a C
5 hirel fpgas desc smd/actel part number cross reference actel part number dscc smd dscc smd (gold leads) (gold leads) (solder dipped) a1010b-pg84b 5962-9096403mxc 5962-9096403mxa a1010b-1pg84b 5962-9096404mxc 5962-9096404mxa a1020b-pg84b 5962-9096503muc 5962-9096503mua a1020b-1pg84b 5962-9096504muc 5962-9096504mua a1020b-cq84b 5962-9096503mtc 5962-9096503mta a1020b-1cq84b 5962-9096504mtc 5962-9096504mta a1240a-pg132b 5962-9322101mxc 5962-9322101mxa a1240a-1pg132b 5962-9322102mxc 5962-9322102mxa a1280a-pg176b 5962-9215601mxc 5962-9215601mxa a1280a-1pg176b 5962-9215602mxc 5962-9215602mxa a1280a-cq172b 5962-9215601myc 5962-9215601mya a1280a-1cq172b 5962-9215602myc 5962-9215602mya a1425a-pg133b 5962-9552001mxc n/a a1425a-1pg133b 5962-9552002mxc n/a a1425a-cq132b 5962-9552001myc n/a a1425a-1cq132b 5962-9552002myc n/a a1460a-pg207b 5962-9550801mxc n/a a1460a-1pg207b 5962-9550802mxc n/a a1460a-cq196b 5962-9550801myc n/a a1460a-1cq196b 5962-9550802myc n/a a14100a-pg257b 5962-9552101mxc n/a a14100a-1pg257b 5962-9552102mxc n/a a14100a-cq256b 5962-9552101myc n/a a14100a-1cq256b 5962-9552102myc n/a A32100DX-cq84b 5962-9875901qxc n/a A32100DX-1cq84b 5962-9857902qxc n/a a32200dx-cq256b 5962-9952701qxc n/a a32200dx-1cq256b 5962-9952702qxc n/a a32200dx-cq208b 5962-9952701qyc n/a a32200dx-1cq208b 5962-9952702qyc n/a
6 product plan applications: c = commercial availability: 4 = available *speed grade: C1 = approx. 15% faster than standard m= military = not planned b = mil-std-883 e = extended flow speed grade application 3200dx family std C1* c m b e A32100DX device 84-pin ceramic quad flat pack (cqfp) 44 444 a32200dx device 208-pin ceramic quad flat pack (cqfp) 44 444 256-pin ceramic quad flat pack (cqfp) 44 444 act 3 family a1425a device 132-pin ceramic quad flat pack (cqfp) 44 4444 133-pin ceramic pin grid array (cpga) 44 4444 a1460a device 196-pin ceramic quad flat pack (cqfp) 44 4444 207-pin ceramic pin grid array (cpga) 44 4444 a14100a device 256-pin ceramic quad flat pack (cqfp) 44 4444 257-pin ceramic pin grid array (cpga) 44 4444 1200xl family a1280xl device 172-pin ceramic quad flat pack (cqfp) 44 444 176-pin ceramic pin grid array (cpga) 44 444 act 2 family a1240a device 132-pin ceramic pin grid array (cpga) 44 444 a1280a device 172-pin ceramic quad flat pack (cqfp) 44 4444 176-pin ceramic pin grid array (cpga) 44 4444 act 1 family a1010b device 84-pin ceramic pin grid array (cpga) 44 444 a1020b device 84-pin ceramic quad flat pack (cqfp) 44 4444 84-pin ceramic pin grid array (cpga) 44 4444
7 hirel fpgas 3200dx device resources act 3 device resources 1200xl device resources act 2 device resources act 1 device resources user i/os fpga device type logic modules gate array equivalent gates cqfp 84-pin 208-pin 256-pin A32100DX 1,362 10,000 60 a32200dx 2,414 20,000 176 202 user i/os fpga device type logic modules gate array equivalent gates cqfp cpga 132-pin 196-pin 256-pin 133-pin 207-pin 257-pin a1425a 310 2,500 100 100 a1460a 848 6,000 168 168 a14100a 1,377 10,000 228 228 user i/os fpga device type logic modules gate array equivalent gates cqfp cpga 172-pin 176-pin a1280xl 1,232 8,000 140 140 user i/os fpga device type logic modules gate array equivalent gates cqfp cpga 172-pin 132-pin 176-pin a1240a 684 4,000 104 a1280a 1,232 8,000 140 140 user i/os fpga device type logic modules gate array equivalent gates cqfp cpga 84-pin 84-pin a1010b 295 1,200 57 a1020b 547 2,000 69 69
8 actel mil-std-883 product flow step screen 883 method 883class b requirement 1. internal visual 2010, test condition b 100% 2. temperature cycling 1010, test condition c 100% 3. constant acceleration 2001, test condition d or e, y 1 , orientation only 100% 4. seal a. fine b. gross 1014 100% 100% 5. visual inspection 2009 100% 6. pre-burn-in electrical parameters in accordance with applicable actel device specification 100% 7. burn-in test 1015, condition d, 160 hours @ 125c or 80 hours @ 150c 100% 8. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 9. percent defective allowable 5% all lots 10. final electrical test a. static tests (1) 25c (subgroup 1, table i) (2) C55c and +125c (subgroups 2, 3, table i) b. functional tests (1) 25c (subgroup 7, table i) (2) C55c and +125c (subgroups 8a and 8b, table i) c. switching tests at 25c (subgroup 9, table i) in accordance with applicable actel device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 11. external visual 2009 100% note: when destructive physical analysis (dpa) is performed on class b devices, the step coverage requirement as specified in method 2018 must be waived.
9 hirel fpgas actel extended flow 1 notes: 1. actel offers the extended flow for customers who require additional screening beyond the requirements of the mil-std-833, cla ss b. actel is compliant to the requirements of mil-std-883, paragraph 1.2.1, and mil-i-38535, appendix a. actel is offering this extended flo w incorporating the majority of the screening procedures as outlined in method 5004 of mil-std-883, class s. the exceptions to me thod 5004 are shown in notes 2 and 3 below. 2. wafer lot acceptance is performed to method 5007; however, the step coverage requirement as specified in method 2018 must be waived. 3. mil-std-883, method 5004 requires 100 percent radiation latch-up testing (method 1020). actel will not be performing any radia tion testing, and this requirement must be waived in its entirety. step screen method require- ment 1. wafer lot acceptance 2 5007 with step coverage waiver all lots 2. destructive in-line bond pull 3 2011, condition d sample 3. internal visual 2010, condition a 100% 4. serialization 100% 5. temperature cycling 1010, condition c 100% 6. constant acceleration 2001, condition d or e, y 1 orientation only 100% 7. particle impact noise detection 2020, condition a 100% 8. radiographic 2012 (one view only) 100% 9. pre-burn-in test in accordance with applicable actel device specification 100% 10. burn-in test 1015, condition d, 240 hours @ 125c minimum 100% 11. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 12. reverse bias burn-in 1015, condition c, 72 hours @ 150c minimum 100% 13. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 14. percent defective allowable (pda) calculation 5%, 3% functional parameters @ 25c all lots 15. final electrical test a. static tests (1) 25c (subgroup 1, table1) (2) C55c and +125c (subgroups 2, 3, table 1) b. functional tests (1) 25c (subgroup 7, table 15) (2) C55c and +125c (subgroups 8a and b, table 1) c. switching tests at 25c (subgroup 9, table 1) in accordance with actel applicable device specification which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 100% 16. seal a. fine b. gross 1014 100% 17. external visual 2009 100%
10 absolute maximum ratings 1 free air temperature range notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. devices should not be operated outside the recommended operating conditions. 2. v pp = v cc , except during device programming. 3. v sv = v cc , except during device programming. 4. v ks = gnd , except during device programming. 5. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5v or less than gnd C 0.5v, the internal protection diode will be forward biased and can draw excessive current. recommended operating conditions notes: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military. 2. all power supplies must be in the recommended operating range. for more information, refer to the power-up design considerations application note at http://www.actel.com/appnotes . electrical specifications notes: 1. actel devices can drive and receive either cmos or ttl signal levels. no assignment of i/os as ttl or cmos is required. 2. tested one output at a time, v cc = min. 3. not tested; for information only. 4. v out = 0v, f = 1 mhz symbol parameter limits units v cc dc supply voltage 2, 3, 4 C0.5 to +7.0 v v i input voltage C0.5 to v cc +0.5 v v o output voltage C0.5 to v cc +0.5 v i io i/o source sink current 5 20 ma t stg storage temperature C65 to +150 c parameter commercial military units temperature range 1 0 to +70 C55 to +125 c power supply tolerance 2 5 10 %v cc symbol parameter test condition commercial military units min. max. min. max. v oh 1, 2 high level output i oh = C4 ma (cmos) 3.7 v i oh = C6 ma (cmos) 3.84 v v ol 1, 2 low level output i ol = +6 ma (cmos) 0.33 0.4 v v ih high level input ttl inputs 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il low level input ttl inputs C0.3 0.8 C0.3 0.8 v i in input leakage v i = v cc or gnd C10 +10 C10 +10 a i oz 3-state output leakage v o = v cc or gnd C10 +10 C10 +10 a c io i/o capacitance 3, 4 10 10 pf i cc(s) standby v cc supply current v i = v cc or gnd, i o = 0 ma act 1 3 20 ma act 2/3/1200xl/3200dx 2 20 ma i cc(d) dynamic v cc supply current see the power dissipation section on page 11.
11 hirel fpgas package thermal characteristics the device junction to case thermal characteristic is q jc , and the junction to ambient air characteristic is q ja . the thermal characteristics for q ja are shown with two different air flow rates. maximum junction temperature is 150c. a sample calculation of the absolute maximum power dissipation allowed for a cpga 176-pin package at military temperature is as follows: power dissipation general power equation p = [i cc standby + i cc active] * v cc + i ol * v ol * n + i oh * (v cc C v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . accurate values for n and m are difficult to determine because they depend on the family type, on the design, and on the system i/o. the power can be divided into two componentsstatic and active. static power component actel fpgas have small static power components that result in power dissipation lower than that of pals or plds. by integrating multiple pals or plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. standby power is calculated below for commercial, worst-case conditions. the static power dissipated by ttl loads depends on the number of outputs driving high or low and the dc load current. again, this value is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33v will generate 42 mw with all outputs driving low, and 140 mw with all outputs driving high. active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissipation is the totempole current in cmos transistor pairs. the net effect can be associated with an equivalent capacitance that package type pin count q jc q ja still air q ja 300 ft/min units ceramic pin grid array 84 132 133 176 207 257 6.0 4.8 4.8 4.6 3.5 2.8 33 25 25 23 21 15 20 16 15 12 10 8 c/w c/w c/w c/w c/w c/w ceramic quad flat pack 84 132 172 196 256 7.8 7.2 6.8 6.4 6.2 40 35 25 23 20 30 25 20 15 10 c/w c/w c/w c/w c/w max. junction temp. (c) C max. military temp. q ja (c/w) ------------------------------------------------------------------------------------------------------------------ 150c C 125c 23c/w ------------------------------------ 1 . 1 w == family i cc v cc power act 3 2 ma 5.25v 10.5 mw 1200xl/3200dx 2 ma 5.25v 10.5 mw act 2 2 ma 5.25v 10.5 mw act 1 3 ma 5.25v 15.8 mw
12 can be combined with frequency and voltage to represent active power dissipation. equivalent capacitance the power dissipated by a cmos circuit can be expressed by equation 1: power (uw) = c eq * v cc 2 * f (1) where: equivalent capacitance is calculated by measuring i cc active at a specified frequency and voltage for each circuit component of interest. measurements are made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency independent so that the results can be used over a wide range of operating conditions. equivalent capacitance values are shown below. ceq values for actel fpgas to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. equation 2 shows a piecewise linear summation over all components that applies to all act 1, 1200xl, 3200dx, act 2, and act 3 devices. since the act 1 family has only one routed array clock, the terms labeled routed_clk2, dedicated_clk, and io_clk do not apply. similarly, the act 2 family has two routed array clocks, and the dedicated_clk and io_clk terms do not apply. for act 3 devices, all terms will apply. power = v cc 2 * [(m * c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 + 0.5 * (s 1 * c eqcd * f s1 ) dedicated_clk + (s 2 * c eqci * f s2 ) io_clk ](2) where: c eq = equivalent capacitance in pf v cc = power supply in volts (v) f = switching frequency in mhz act 3 1200xl 3200dx act 2 act 1 modules (c eqm ) 6.7 5.2 5.8 3.7 input buffers (c eqi ) 7.2 11.6 12.9 22.1 output buffers (c eqo ) 10.4 23.8 23.8 31.2 routed array clock buffer loads (c eqcr ) 1.6 3.5 3.9 4.6 dedicated clock buffer loads (c eqcd ) 0.7n/an/an/a i/o clock buffer loads (c eqci ) 0.9n/an/an/a m = number of logic modules switching at f m n = number of input buffers switching at f n p = number of output buffers switching at f p q 1 = number of clock loads on the first routed array clock (all families) q 2 = number of clock loads on the second routed array clock (act 2, 1200xl, 3200dx, act 3 only) r 1 = fixed capacitance due to first routed array clock (all families) r 2 = fixed capacitance due to second routed array clock (act 2, 1200xl, 3200dx, act 3 only) s 1 = fixed number of clock loads on the dedicated array clock (act 3 only) s 2 = fixed number of clock loads on the dedicated i/o clock (act 3 only) c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c eqcd = equivalent capacitance of dedicated array clock in pf c eqci = equivalent capacitance of dedicated i/o clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz (all families) f q2 = average second routed array clock rate in mhz (act 2, 1200xl, 3200dx, act 3 only) f s1 = average dedicated array clock rate in mhz (act 3 only) f s2 = average dedicated i/o clock rate in mhz (act 3 only)
13 hirel fpgas fixed capacitance values for actel fpgas (pf) fixed clock loads (s 1 /s 2 act 3 only) determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data values input to the circuit. the guidelines in the table below are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. device type r 1 routed_clk1 r 2 routed_clk2 a1010b 41 n/a a1020b 69 n/a a1240a 134 134 a1280a 168 168 a1280xl 168 168 a1425a 75 75 a1460a 165 165 a14100a 195 195 A32100DX 178 178 a32200dx 230 230 device type s 1 clock loads on dedicated array clock s 2 clock loads on dedicated i/o clock a1425a 160 100 a1460a 432 168 a14100a 697 228 type act 3 3200dx/act 2/1200xl act 1 logic modules (m) 80% of modules 80% of modules 90% of modules input switching (n) # inputs/4 # inputs/4 # inputs/4 outputs switching (p) #outputs/4 #outputs/4 #outputs/4 first routed array clock loads (q 1 ) 40% of sequential modules 40% of sequential modules 40% of modules second routed array clock loads (q 2 ) 40% of sequential modules 40% of sequential modules n/a load capacitance (c l ) 35 pf 35 pf 35 pf average logic module switching rate (f m ) f/10 f/10 f/10 average input switching rate (f n ) f/5 f/5 f/5 average output switching rate (f p ) f/10 f/10 f/10 average first routed array clock rate (f q1 )f/2 f f average second routed array clock rate (f q2 ) f/2 f/2 n/a average dedicated array clock rate (f s1 )f n/a n/a average dedicated i/o clock rate (f s2 )f n/a n/a
14 3200dx timing model (logic functions using array clocks)* *values shown for A32100DXC1 at worst-case military conditions. output delays internal delays input delays t inh = 0.0 ns t insu = 0.7 ns i/o module d q t ingo = 4.0 ns t inpy = 1.9 ns t ird1 = 2.2 ns combinatorial module t pd = 3.1 ns sequential logic module i/o module t rd1 = 1.3 ns t dlh = 6.3 ns i/o module array clocks f max = 140 mhz combin- atorial logic included in t sud d q d q t lh = 0.0 ns t lsu = 0.4 ns t ghl = 12.4 ns t dlh = 6.3 ns t enhz = 11.5 ns t rd1 = 1.3 ns t co = 3.1 ns t su = 0.5 ns t hd = 0.0 ns predicted routing delays g g decode module t pdd = 3.3 ns t rdd = 0.5 ns t rd2 = 1.9 ns t rd4 = 3.3 ns t ckh = 6.5 ns
15 hirel fpgas 3200dx timing model (logic functions using quadrant clocks)* * values shown for A32100DXC1 at worst-case military conditions. ** load dependent. output delays internal delays input delays t inh = 0.0 ns t insu = 0.7 ns i/o module d q t ingo = 4.0 ns t inpy = 1.9 ns t ird1 = 2.2 ns combinatorial module t pd = 3.1 ns sequential logic module i/o module t rd1 = 1.3 ns t dlh = 6.3 ns i/o module quadrant clocks f max = 100 mhz combin- atorial logic included in t sud d q d q t lh = 0.0 ns t lsu = 0.4 ns t ghl = 12.4 ns t dlh = 6.3 ns t enhz = 11.5 ns t rd1 = 1.3 ns t co = 3.1 ns t su = 0.5 ns t hd = 0.0 ns predicted routing delays g g decode module t pdd = 3.3 ns t rdd = 0.5 ns t rd2 = 1.9 ns t rd4 = 3.3 ns t ckh = 12 ns**
16 3200dx timing model (sram functions)* *values shown for A32100DXC1 at worst-case military conditions. t inh = 0.0 ns t insu = 0.7 ns input delays i/o module d q t ingo = 4.0 ns t inpy = 1.9 ns t ird1 = 2.2 ns array clocks f max = 140 mhz g t ghl = 12.4 ns t lsu = 0.4 ns i/o module d q t lh = 0.0 ns t dlh = 6.3 ns g wd [7:0] wrad [5:0] blken wen wclk t adsu = 2.1 ns t adh = 0.0 ns t wensu = 3.5 ns t bens = 3.6 ns rd [7:0] rdad [5:0] ren rclk t adsu = 2.1 ns t adh = 0.0 ns t rensu = 0.8 ns t rd1 = 1.3 ns predicted routing delays t rco = 4.4 ns
17 hirel fpgas 1200xl timing model* *values shown for a1280xlC1 at worst-case military conditions. ? input module predicted routing delay. output delays internal delays input delays t inh = 0.0 ns t insu = 0.4 ns i/o module d q t ingl = 3.7 ns t inyl = 1.7 ns t ird2 = 5.2 ns ? combinatorial logic module t pd = 3.7 ns sequential logic module i/o module t rd1 = 1.7 ns t dlh = 6.6 ns i/o module array clocks f max = 110 mhz combin- atorial logic included in t sud d q d q t outh = 0.0 ns t outsu = 0.4 ns t glh = 5.9 ns t dlh = 6.6 ns t enhz = 7.5 ns t rd1 = 1.7 ns t co = 3.7 ns t su = 0.4 ns t hd = 0.0 ns t rd4 = 3.7 ns t rd8 = 7.0 ns predicted routing delays t ckh = 7.1 ns g g fo = 256 t rd2 = 2.5 ns t lco = 10.7 ns (64 loads, pad-pad)
18 parameter measurement output buffer delays ac test load input buffer delays combinatorial macro delays pa d to ac test loads (shown below) d e tribuff in v cc gnd 50% pa d v ol v oh 1.5v t dlh 50% 1.5v t dhl e v cc gnd 50% pa d v ol 1.5v t enzl 50% 10% t enlz e v cc gnd 50% pa d gnd v oh 1.5v t enzh 50% 90% t enhz v cc pad load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 50 pf to the output under test v cc gnd 50 pf to the output under test r to v cc for t plz /t pzl r to gnd for t phz /t pzh r = 1 k w pa d y inbuf pa d 3v 0v 1.5v y gnd v cc 50% t inyh 1.5v 50% t inyl pad s a b y s, a, or b y gnd v cc 50% t plh y gnd gnd v cc 50% 50% 50% v cc 50% 50% t phl t phl t plh
19 hirel fpgas sequential timing characteristics flip-flops and latches (act 3) note: 1. d represents all data functions involving a, b, and s for multiplexed flip-flops. (positive edge triggered) d e clk clr y d 1 g, clk e q clr t wclka t wasyn t hd t suena t sud t clr t a t co t hena
20 sequential timing characteristics (continued) flip-flops and latches (1200xl/3200dx, act 2, and act 1) note: 1. d represents all data functions involving a, b, and s for multiplexed flip-flops. (positive edge triggered) d e clk clr pre y d 1 g, clk e q pre, clr t wclka t wasyn t hd t suena t sud t rs t a t co t hena
21 hirel fpgas sequential timing characteristics (continued) input buffer latches (act 2 and 1200xl/3200dx) output buffer latches (act 2 and 1200xl/3200dx) g pad pad clk pa d g clk t inh clkbuf t insu t suext t hext ibdl d g t outsu t outh pa d obdlhs d g
22 decode module timing sram timing characteristics aCg, h y t plh 50% v cc v cc t phl y a b c d e f g h wrad [5:0] blken wen wclk rdad [5:0] lew ren rclk rd [7:0] wd [7:0] write port read port ram array 32x8 or 64x4 (256 bits)
23 hirel fpgas dual-port sram timing waveforms 3200dx sram write operation note: identical timing for falling-edge clock. 3200dx sram synchronous read operation note: identical timing for falling-edge clock. wclk wd[7:0] wrad[5:0] wen blken valid valid t rckhl t rckhl t wensu t bensu t wenh t benh t adsu t adh rclk ren rdad[5:0] rd[7:0] old data valid t rckhl t ckhl t renh t rco t adh t doh t adsu new data t rensu
24 3200dx sram asynchronous read operationtype 1 (read address controlled) 3200dx sram asynchronous read operationtype 2 (write address controlled) rdad[5:0] rd[7:0] data 1 t rdadv t doh addr2 addr1 data 2 t rpd wen wd[7:0] wclk rd[7:0] old data valid t wenh t rpd t wensu new data t doh t adsu wrad[5:0] blken t adh
25 hirel fpgas act 1 timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays t pd1 single module 4.7 5.5 ns t pd2 dual module macros 10.8 12.7 ns t co sequential clk to q 4.7 5.5 ns t go latch g to q 4.7 5.5 ns t rs flip-flop (latch) reset to q 4.7 5.5 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.5 1.7 ns t rd2 fo=2 routing delay 2.3 2.7 ns t rd3 fo=3 routing delay 3.4 4.0 ns t rd4 fo=4 routing delay 5.0 5.9 ns t rd8 fo=8 routing delay 10.6 12.5 ns logic module sequential timing 2 t sud flip-flop (latch) data input setup 8.8 10.4 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 8.8 10.4 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 10.9 12.9 ns t wasyn flip-flop (latch) asynchronous pulse width 10.9 12.9 ns t a flip-flop clock input period 23.2 27.3 ns f max flip-flop (latch) clock frequency 44 37 mhz input module propagation delays t inyh pad to y high 4.9 5.8 ns t inyl pad to y low 4.9 5.8 ns input module predicted routing delays 1, 3 t ird1 fo=1 routing delay 1.5 1.7 ns t ird2 fo=2 routing delay 2.3 2.7 ns t ird3 fo=3 routing delay 3.4 4.0 ns t ird4 fo=4 routing delay 5.0 5.9 ns t ird8 fo=8 routing delay 10.6 12.5 ns notes: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. setup times assume fanout of 3. further derating information can be obtained from the directtime analyzer utility. 3. optimization techniques may further reduce delays by 0 to 4 ns.
26 act 1 timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units global clock network t ckh input low to high fo = 16 fo = 128 7.8 8.9 9.2 10.5 ns t ckl input high to low fo = 16 fo = 128 10.3 11.2 12.1 13.2 ns t pwh minimum pulse width high fo = 16 fo = 128 10.4 10.9 12.2 12.9 ns t pwl minimum pulse width low fo = 16 fo = 128 10.4 10.9 12.2 12.9 ns t cksw maximum skew fo = 16 fo = 128 1.9 2.9 2.2 3.4 ns t p minimum period fo = 16 fo = 128 21.7 23.2 25.6 27.3 ns f max maximum frequency fo = 16 fo = 128 46 44 40 37 mhz ttl output module timing 1 t dlh data to pad high 12.1 14.2 ns t dhl data to pad low 13.8 16.3 ns t enzh enable pad z to high 12.0 14.1 ns t enzl enable pad z to low 14.6 17.1 ns t enhz enable pad high to z 16.0 18.8 ns t enlz enable pad low to z 14.5 17.0 ns d tlh delta low to high 0.09 0.11 ns/pf d thl delta high to low 0.12 0.15 ns/pf cmos output module timing 1 t dlh data to pad high 15.1 17.7 ns t dhl data to pad low 11.5 13.6 ns t enzh enable pad z to high 12.0 14.1 ns t enzl enable pad z to low 14.6 17.1 ns t enhz enable pad high to z 16.0 18.8 ns t enlz enable pad low to z 14.5 17.0 ns d tlh delta low to high 0.16 0.18 ns/pf d thl delta high to low 0.09 0.11 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
27 hirel fpgas a1240a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd1 single module 5.2 6.1 ns t co sequential clk to q 5.2 6.1 ns t go latch g to q 5.2 6.1 ns t rs flip-flop (latch) reset to q 5.2 6.1 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.9 2.2 ns t rd2 fo=2 routing delay 2.4 2.8 ns t rd3 fo=3 routing delay 3.1 3.7 ns t rd4 fo=4 routing delay 4.3 5.0 ns t rd8 fo=8 routing delay 6.6 7.7 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input setup 0.5 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 1.3 1.3 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 7.4 8.1 ns t wasyn flip-flop (latch) asynchronous pulse width 7.4 8.1 ns t a flip-flop clock input period 14.8 18.6 ns t inh input buffer latch hold 2.5 2.5 ns t insu input buffer latch setup C3.5 C3.5 ns t outh output buffer latch hold 0.0 0.0 ns t outsu output buffer latch setup 0.5 0.5 ns f max flip-flop (latch) clock frequency 63 54 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external set up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time.
28 a1240a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units input module propagation delays t inyh pad to y high 4.0 4.7 ns t inyl pad to y low 3.6 4.3 ns t ingh g to y high 6.9 8.1 ns t ingl g to y low 6.6 7.7 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 5.8 6.9 ns t ird2 fo=2 routing delay 6.7 7.8 ns t ird3 fo=3 routing delay 7.5 8.8 ns t ird4 fo=4 routing delay 8.2 9.7 ns t ird8 fo=8 routing delay 10.9 12.9 ns global clock network t ckh input low to high fo = 32 fo = 256 13.3 16.3 15.7 19.2 ns t ckl input high to low fo = 32 fo = 256 13.3 16.5 15.7 19.5 ns t pwh minimum pulse width high fo = 32 fo = 256 5.7 6.0 6.7 7.1 ns t pwl minimum pulse width low fo = 32 fo = 256 5.7 6.0 6.7 7.1 ns t cksw maximum skew fo = 32 fo = 256 0.6 3.1 0.6 3.1 ns t suext input latch external setup fo = 32 fo = 256 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 256 8.6 13.8 8.6 13.8 ns t p minimum period fo = 32 fo = 256 11.5 12.2 13.5 14.3 ns f max maximum frequency fo = 32 fo = 256 87 82 74 70 mhz note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. optimization techniques may further reduc e delays by 0 to 4 ns.
29 hirel fpgas a1240a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units ttl output module timing 1 t dlh data to pad high 11.0 13.0 ns t dhl data to pad low 13.9 16.4 ns t enzh enable pad z to high 12.3 14.4 ns t enzl enable pad z to low 16.1 19.0 ns t enhz enable pad high to z 9.8 11.5 ns t enlz enable pad low to z 11.5 13.6 ns t glh g to pad high 12.4 14.6 ns t ghl g to pad low 15.5 18.2 ns d tlh delta low to high 0.09 0.11 ns/pf d thl delta high to low 0.17 0.20 ns/pf cmos output module timing 1 t dlh data to pad high 14.0 16.5 ns t dhl data to pad low 11.7 13.7 ns t enzh enable pad z to high 12.3 14.4 ns t enzl enable pad z to low 16.1 19.0 ns t enhz enable pad high to z 9.8 11.5 ns t enlz enable pad low to z 11.5 13.6 ns t glh g to pad high 12.4 14.6 ns t ghl g to pad low 15.5 18.2 ns d tlh delta low to high 0.17 0.20 ns/pf d thl delta high to low 0.12 0.15 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
30 a1280a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd1 single module 5.2 6.1 ns t co sequential clk to q 5.2 6.1 ns t go latch g to q 5.2 6.1 ns t rs flip-flop (latch) reset to q 5.2 6.1 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 2.4 2.8 ns t rd2 fo=2 routing delay 3.4 4.0 ns t rd3 fo=3 routing delay 4.2 4.9 ns t rd4 fo=4 routing delay 5.1 6.0 ns t rd8 fo=8 routing delay 9.2 10.8 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input setup 0.5 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 1.3 1.3 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 7.4 8.6 ns t wasyn flip-flop (latch) asynchronous pulse width 7.4 8.6 ns t a flip-flop clock input period 16.4 22.1 ns t inh input buffer latch hold 2.5 2.5 ns t insu input buffer latch setup C3.5 C3.5 ns t outh output buffer latch hold 0.0 0.0 ns t outsu output buffer latch setup 0.5 0.5 ns f max flip-flop (latch) clock frequency 60 41 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external set up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time.
31 hirel fpgas a1280a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units input module propagation delays t inyh pad to y high 4.0 4.7 ns t inyl pad to y low 3.6 4.3 ns t ingh g to y high 6.9 8.1 ns t ingl g to y low 6.6 7.7 ns input module predicted routing delays 1 t rd1 fo=1 routing delay 6.2 7.3 ns t rd2 fo=2 routing delay 7.2 8.4 ns t rd3 fo=3 routing delay 7.7 9.1 ns t rd4 fo=4 routing delay 8.9 10.5 ns t rd8 fo=8 routing delay 12.9 15.2 ns global clock network t ckh input low to high fo = 32 fo = 384 13.3 17.9 15.7 21.1 ns t ckl input high to low fo = 32 fo = 384 13.3 18.2 15.7 21.4 ns t pwh minimum pulse width high fo = 32 fo = 384 6.9 7.9 8.1 9.3 ns t pwl minimum pulse width low fo = 32 fo = 384 6.9 7.9 8.1 9.3 ns t cksw maximum skew fo = 32 fo = 384 0.6 3.1 0.6 3.1 ns t suext input latch external setup fo = 32 fo = 384 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 384 8.6 13.8 8.6 13.8 ns t p minimum period fo = 32 fo = 384 13.7 16.0 16.2 18.9 ns f max maximum frequency fo = 32 fo = 384 73 63 62 53 mhz note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. optimization techniques may further reduce dela ys by 0 to 4 ns.
32 a1280a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units ttl output module timing 1 t dlh data to pad high 11.0 13.0 ns t dhl data to pad low 13.9 16.4 ns t enzh enable pad z to high 12.3 14.4 ns t enzl enable pad z to low 16.1 19.0 ns t enhz enable pad high to z 9.8 11.5 ns t enlz enable pad low to z 11.5 13.6 ns t glh g to pad high 12.4 14.6 ns t ghl g to pad low 15.5 18.2 ns d tlh delta low to high 0.09 0.11 ns/pf d thl delta high to low 0.17 0.20 ns/pf cmos output module timing 1 t dlh data to pad high 14.0 16.5 ns t dhl data to pad low 11.7 13.7 ns t enzh enable pad z to high 12.3 14.4 ns t enzl enable pad z to low 16.1 19.0 ns t enhz enable pad high to z 9.8 11.5 ns t enlz enable pad low to z 11.5 13.6 ns t glh g to pad high 12.4 14.6 ns t ghl g to pad low 15.5 18.2 ns d tlh delta low to high 0.17 0.20 ns/pf d thl delta high to low 0.12 0.15 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
33 hirel fpgas a1280xl timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd1 single module 3.7 4.3 ns t co sequential clk to q 3.7 4.3 ns t go latch g to q 3.7 4.3 ns t rs flip-flop (latch) reset to q 3.7 4.3 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.7 2.1 ns t rd2 fo=2 routing delay 2.5 3.0 ns t rd3 fo=3 routing delay 3.1 3.6 ns t rd4 fo=4 routing delay 3.7 4.3 ns t rd8 fo=8 routing delay 7.0 8.3 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input setup 0.4 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 1.1 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 5.3 6.1 ns t wasyn flip-flop (latch) asynchronous pulse width 5.3 6.1 ns t a flip-flop clock input period 10.7 12.3 ns t inh input buffer latch hold 0.0 0.0 ns t insu input buffer latch setup 0.4 0.4 ns t outh output buffer latch hold 0.0 0.0 ns t outsu output buffer latch setup 0.4 0.4 ns f max flip-flop (latch) clock frequency 90 75 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external set up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time.
34 a1280xl timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units input module propagation delays t inyh pad to y high 1.5 1.7 ns t inyl pad to y low 1.7 2.1 ns t ingh g to y high 2.8 3.3 ns t ingl g to y low 3.7 4.3 ns input module predicted routing delays 1 t rd1 fo=1 routing delay 4.6 5.3 ns t rd2 fo=2 routing delay 5.2 6.1 ns t rd3 fo=3 routing delay 5.5 6.5 ns t rd4 fo=4 routing delay 6.4 7.5 ns t rd8 fo=8 routing delay 9.2 10.8 ns global clock network t ckh input low to high fo = 32 fo = 384 7.1 8.0 8.4 9.5 ns t ckl input high to low fo = 32 fo = 384 7.0 8.0 8.3 9.5 ns t pwh minimum pulse width high fo = 32 fo = 384 4.3 4.8 5.3 5.7 ns t pwl minimum pulse width low fo = 32 fo = 384 4.3 4.8 5.3 5.7 ns t cksw maximum skew fo = 32 fo = 384 1.1 1.1 1.2 1.2 ns t suext input latch external setup fo = 32 fo = 384 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 384 3.6 4.6 4.2 5.3 ns t p minimum period fo = 32 fo = 384 9.1 9.8 10.7 11.8 ns f max maximum frequency fo = 32 fo = 384 110 100 90 85 mhz note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. optimization techniques may further reduce dela ys by 0 to 4 ns.
35 hirel fpgas a1280xl timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units ttl output module timing 1 t dlh data to pad high 5.3 6.2 ns t dhl data to pad low 5.7 6.6 ns t enzh enable pad z to high 5.3 6.2 ns t enzl enable pad z to low 5.8 6.8 ns t enhz enable pad high to z 7.5 8.9 ns t enlz enable pad low to z 7.5 8.9 ns t glh g to pad high 5.9 6.9 ns t ghl g to pad low 6.6 7.8 ns d tlh delta low to high 0.05 0.06 ns/pf d thl delta high to low 0.05 0.09 ns/pf cmos output module timing 1 t dlh data to pad high 6.6 7.9 ns t dhl data to pad low 4.7 5.5 ns t enzh enable pad z to high 5.3 6.2 ns t enzl enable pad z to low 5.8 6.8 ns t enhz enable pad high to z 7.5 8.9 ns t enlz enable pad low to z 7.5 8.9 ns t glh g to pad high 5.9 6.9 ns t ghl g to pad low 6.6 7.8 ns d tlh delta low to high 0.07 0.09 ns/pf d thl delta high to low 0.06 0.09 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
36 a1425a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock to q 3.0 3.5 ns t clr asynchronous clear to q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 0.9 1.0 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wasyn asynchronous pulse width 3.8 4.4 ns t wclka flip-flop clock pulse width 3.8 4.4 ns t a flip-flop clock input period 7.9 9.3 ns f max flip-flop clock frequency 125 100 mhz input module propagation delays t iny input data pad to y 4.2 4.9 ns t icky input reg ioclk pad to y 7.0 8.2 ns t ocky output reg ioclk pad to y 7.0 8.2 ns t iclry input asynchronous clear to y 7.0 8.2 ns t oclry output asynchronous clear to y 7.0 8.2 ns input module predicted routing delays 1, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may further reduce delays by 0 to 4 ns.
37 hirel fpgas a1425a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input f-f data hold (w.r.t. ioclk pad) 0.0 0.0 ns t insu input f-f data setup (w.r.t. ioclk pad) 2.1 2.4 ns t ideh input data enable hold (w.r.t. ioclk pad) 0.0 0.0 ns t idesu input data enable setup (w.r.t. ioclk pad) 8.7 10.0 ns t outh output f-f data hold (w.r.t. ioclk pad) 1.1 1.2 ns t outsu output f-f data setup (w.r.t. ioclk pad) 1.1 1.2 ns t odeh output data enable hold (w.r.t. ioclk pad) 0.5 0.6 ns t odesu output data enable setup (w.r.t. ioclk pad) 2.0 2.4 ns ttl output module timing 1 t dhs data to pad, high slew 7.5 8.9 ns t dls data to pad, low slew 11.9 14.0 ns t enzhs enable to pad, z to h/l, high slew 6.0 7.0 ns t enzls enable to pad, z to h/l, low slew 10.9 12.8 ns t enhsz enable to pad, h/l to z, high slew 9.9 11.6 ns t enlsz enable to pad, h/l to z, low slew 9.9 11.6 ns t ckhs ioclk pad to pad h/l, high slew 10.5 11.6 ns t ckls ioclk pad to pad h/l, low slew 15.7 17.4 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf note: 1. delays based on 35 pf loading.
38 a1425a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units cmos output module timing 1 t dhs data to pad, high slew 9.2 10.8 ns t dls data to pad, low slew 17.3 20.3 ns t enzhs enable to pad, z to h/l, high slew 7.7 9.1 ns t enzls enable to pad, z to h/l, low slew 13.1 15.5 ns t enhsz enable to pad, h/l to z, high slew 9.9 11.6 ns t enlsz enable to pad, h/l to z, low slew 10.5 11.6 ns t ckhs ioclk pad to pad h/l, high slew 12.5 13.7 ns t ckls ioclk pad to pad h/l, low slew 18.1 20.1 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.0 3.5 ns t iopwh minimum pulse width high 3.9 4.4 ns t iopwl minimum pulse width low 3.9 4.4 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.5 0.5 ns t iop minimum period 7.9 9.3 ns f iomax maximum frequency 125 100 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 4.6 5.3 ns t hckl input high to low (pad to s-module input) 4.6 5.3 ns t hpwh minimum pulse width high 3.9 4.4 ns t hpwl minimum pulse width low 3.9 4.4 ns t hcksw maximum skew 0.4 0.4 ns t hp minimum period 7.9 9.3 ns f hmax maximum frequency 125 100 mhz notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
39 hirel fpgas a1425a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units routed array clock networks t rckh input low to high (fo=64) 5.5 6.4 ns t rckl input high to low (fo=64) 6.0 7.0 ns t rpwh min. pulse width high (fo=64) 4.9 5.7 ns t rpwl min. pulse width low (fo=64) 4.9 5.7 ns t rcksw maximum skew (fo=128) 1.1 1.2 ns t rp minimum period (fo=64) 10.1 11.6 ns f rmax maximum frequency (fo=64) 100 85 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew 0.0 3.0 0.0 3.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns
40 a1460a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock to q 3.0 3.5 ns t clr asynchronous clear to q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 0.9 1.0 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wasyn asynchronous pulse width 4.8 5.6 ns t wclka flip-flop clock pulse width 4.8 5.6 ns t a flip-flop clock input period 9.9 11.6 ns f max flip-flop clock frequency 100 85 mhz input module propagation delays t iny input data pad to y 4.2 4.9 ns t icky input reg ioclk pad to y 7.0 8.2 ns t ocky output reg ioclk pad to y 7.0 8.2 ns t iclry input asynchronous clear to y 7.0 8.2 ns t oclry output asynchronous clear to y 7.0 8.2 ns input module predicted routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may further reduce delays by 0 to 4 ns.
41 hirel fpgas a1460a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input f-f data hold (w.r.t. ioclk pad) 0.0 0.0 ns t insu input f-f data setup (w.r.t. ioclk pad) 2.1 2.4 ns t ideh input data enable hold (w.r.t. ioclk pad) 0.0 0.0 ns t idesu input data enable setup (w.r.t. ioclk pad) 8.7 10.0 ns t outh output f-f data hold (w.r.t. ioclk pad) 1.1 1.2 ns t outsu output f-f data setup (w.r.t. ioclk pad) 1.1 1.2 ns t odeh output data enable hold (w.r.t. ioclk pad) 0.5 0.6 ns t odesu output data enable setup (w.r.t. ioclk pad) 2.0 2.4 ns ttl output module timing 1 t dhs data to pad, high slew 7.5 8.9 ns t dls data to pad, low slew 11.9 14.0 ns t enzhs enable to pad, z to h/l, high slew 6.0 7.0 ns t enzls enable to pad, z to h/l, low slew 10.9 12.8 ns t enhsz enable to pad, h/l to z, high slew 11.5 13.5 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 11.6 13.4 ns t ckls ioclk pad to pad h/l, low slew 17.8 19.8 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf note: 1. delays based on 35 pf loading.
42 a1460a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units cmos output module timing 1 t dhs data to pad, high slew 9.2 10.8 ns t dls data to pad, low slew 17.3 20.3 ns t enzhs enable to pad, z to h/l, high slew 7.7 9.1 ns t enzls enable to pad, z to h/l, low slew 13.1 15.5 ns t enhsz enable to pad, h/l to z, high slew 10.9 12.8 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 14.1 16.0 ns t ckls ioclk pad to pad h/l, low slew 20.2 22.4 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.5 4.1 ns t iopwh minimum pulse width high 4.8 5.7 ns t iopwl minimum pulse width low 4.8 5.7 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.9 1.0 ns t iop minimum period 9.9 11.6 ns f iomax maximum frequency 100 85 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 5.5 6.4 ns t hckl input high to low (pad to s-module input) 5.5 6.4 ns t hpwh minimum pulse width high 4.8 5.7 ns t hpwl minimum pulse width low 4.8 5.7 ns t hcksw maximum skew 0.9 1.0 ns t hp minimum period 9.9 11.6 ns f hmax maximum frequency 100 85 mhz notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
43 hirel fpgas a1460a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units routed array clock networks t rckh input low to high (fo=256) 9.0 10.5 ns t rckl input high to low (fo=256) 9.0 10.5 ns t rpwh min. pulse width high (fo=256) 6.3 7.1 ns t rpwl min. pulse width low (fo=256) 6.3 7.1 ns t rcksw maximum skew (fo=128) 1.9 2.1 ns t rp minimum period (fo=256) 12.9 14.5 ns f rmax maximum frequency (fo=256) 75 65 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew 0.0 5.0 0.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns
44 a14100a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock to q 3.0 3.5 ns t clr asynchronous clear to q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 1.0 1.0 ns t hd flip-flop (latch) data input hold 0.6 0.6 ns t suena flip-flop (latch) enable setup 1.0 1.0 ns t hena flip-flop (latch) enable hold 0.6 0.6 ns t wasyn asynchronous pulse width 4.8 5.6 ns t wclka flip-flop clock pulse width 4.8 5.6 ns t a flip-flop clock input period 9.9 11.6 ns f max flip-flop clock frequency 100 85 mhz input module propagation delays t iny input data pad to y 4.2 4.9 ns t icky input reg ioclk pad to y 7.0 8.2 ns t ocky output reg ioclk pad to y 7.0 8.2 ns t iclry input asynchronous clear to y 7.0 8.2 ns t oclry output asynchronous clear to y 7.0 8.2 ns input module predicted routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may further reduce delays by 0 to 4 ns.
45 hirel fpgas a14100a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input f-f data hold (w.r.t. ioclk pad) 0.0 0.0 ns t insu input f-f data setup (w.r.t. ioclk pad) 2.1 2.4 ns t ideh input data enable hold (w.r.t. ioclk pad) 0.0 0.0 ns t idesu input data enable setup (w.r.t. ioclk pad) 8.7 10.0 ns t outh output f-f data hold (w.r.t. ioclk pad) 1.2 1.2 ns t outsu output f-f data setup (w.r.t. ioclk pad) 1.2 1.2 ns t odeh output data enable hold (w.r.t. ioclk pad) 0.6 0.6 ns t odesu output data enable setup (w.r.t. ioclk pad) 2.4 2.4 ns ttl output module timing 1 t dhs data to pad, high slew 7.5 8.9 ns t dls data to pad, low slew 11.9 14.0 ns t enzhs enable to pad, z to h/l, high slew 6.0 7.0 ns t enzls enable to pad, z to h/l, low slew 10.9 12.8 ns t enhsz enable to pad, h/l to z, high slew 11.9 14.0 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 12.2 14.0 ns t ckls ioclk pad to pad h/l, low slew 17.8 17.8 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf note: 1. delays based on 35 pf loading.
46 a14100a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units cmos output module timing 1 t dhs data to pad, high slew 9.2 10.8 ns t dls data to pad, low slew 17.3 20.3 ns t enzhs enable to pad, z to h/l, high slew 7.7 9.1 ns t enzls enable to pad, z to h/l, low slew 13.1 15.5 ns t enhsz enable to pad, h/l to z, high slew 11.6 14.0 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 14.4 16.0 ns t ckls ioclk pad to pad h/l, low slew 20.2 22.4 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.5 4.1 ns t iopwh minimum pulse width high 4.8 5.7 ns t iopwl minimum pulse width low 4.8 5.7 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.9 1.0 ns t iop minimum period 9.9 11.6 ns f iomax maximum frequency 100 85 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 5.5 6.4 ns t hckl input high to low (pad to s-module input) 5.5 6.4 ns t hpwh minimum pulse width high 4.8 5.7 ns t hpwl minimum pulse width low 4.8 5.7 ns t hcksw maximum skew 0.9 1.0 ns t hp minimum period 9.9 11.6 ns f hmax maximum frequency 100 85 mhz notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
47 hirel fpgas a14100a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units routed array clock networks t rckh input low to high (fo=256) 9.0 10.5 ns t rckl input high to low (fo=256) 9.0 10.5 ns t rpwh min. pulse width high (fo=256) 6.3 7.1 ns t rpwl min. pulse width low (fo=256) 6.3 7.1 ns t rcksw maximum skew (fo=128) 1.9 2.1 ns t rp minimum period (fo=256) 12.9 14.5 ns f rmax maximum frequency (fo=256) 75 65 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.5 0.0 3.5 ns t iorcksw i/o clock to r-clock skew 0.0 5.0 0.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns
48 A32100DX timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module combinatorial functions t pd internal array module delay 3.1 4.1 ns t pdd internal decode module delay 3.3 4.3 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.3 1.8 ns t rd2 fo=2 routing delay 1.9 2.6 ns t rd3 fo=3 routing delay 2.6 3.4 ns t rd4 fo=4 routing delay 3.3 4.3 ns t rd5 fo=8 routing delay 0.6 0.8 ns t rdd decode-to-output routing delay 0.5 0.6 ns logic module sequential timing t co flip-flop clock-to-output 3.1 4.1 ns t go latch gate-to-output 3.1 4.1 ns t su flip-flop (latch) setup time 0.5 0.6 ns t h flip-flop (latch) hold time 0.0 0.0 ns t ro flip-flop (latch) reset to output 3.1 4.1 ns t suena flip-flop (latch) enable setup 0.9 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.3 5.8 ns t wasyn flip-flop (latch) asynchronous pulse width 5.6 7.5 ns note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
49 hirel fpgas A32100DX timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units synchronous sram operations t rc read cycle time 8.8 11.8 ns t wc write cycle time 8.8 11.8 ns t rckhl clock high/low time 4.4 5.9 ns t rco data valid after clock high/low 4.4 5.9 ns t adsu address/data setup time 2.1 2.8 ns t adh address/data hold time 0.0 0.0 ns t rensu read enable setup 0.8 1.1 ns t renh read enable hold 4.4 5.9 ns t wensu write enable setup 3.5 4.7 ns t wenh write enable hold 0.0 0.0 ns t bens block enable setup 3.6 4.8 ns t benh block enable hold 0.0 0.0 ns asynchronous sram operations t rpd asynchronous access time 10.6 14.1 ns t rdadv read address valid 11.5 15.3 ns t adsu address/data setup time 2.1 2.8 ns t adh address/data hold time 0.0 0.0 ns t rensua read enable setup to address valid 0.8 1.1 ns t renha read enable hold 4.4 5.9 ns t wensu write enable setup 3.5 4.7 ns t wenh write enable hold 0.0 0.0 ns t doh data out hold time 1.6 2.1 ns
50 A32100DX timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units input module propagation delays t inpy input data pad to y 1.9 2.6 ns t ingo input latch gate-to-output 4.0 5.3 ns t inh input latch hold 0.0 0.0 ns t insu input latch setup 0.7 0.9 ns t ila latch active pulse width 6.1 8.1 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 2.2 2.9 ns t ird2 fo=2 routing delay 2.8 3.8 ns t ird3 fo=3 routing delay 3.5 4.7 ns t ird4 fo=4 routing delay 3.5 4.7 ns t ird8 fo=8 routing delay 5.6 7.5 ns global clock network t ckh input low to high fo=32 fo=635 6.5 7.9 8.7 10.6 ns ns t ckl input high to low fo=32 fo=635 6.6 8.8 8.8 11.8 ns ns t pwh minimum pulse width high fo=32 fo=635 4.1 4.6 5.5 6.1 ns ns t pwl minimum pulse width low fo=32 fo=635 4.1 4.6 5.5 6.1 ns ns t cksw maximum skew fo=32 fo=635 1.8 1.8 2.4 2.4 ns ns t suext input latch external setup fo=32 fo=635 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 3.0 3.8 4.0 5.1 ns ns t p minimum period (1/fmax) fo=32 fo=635 7.1 7.9 9.5 10.5 ns ns f hmax maximum datapath frequency fo=32 fo=635 140 126 105 95 mhz mhz note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. optimization techniques may further reduc e delays by 0 to 4 ns.
51 hirel fpgas A32100DX timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units ttl output module timing 1 t dlh data to pad high 5.1 6.8 ns t dhl data to pad low 6.3 8.3 ns t enzh enable pad z to high 6.6 8.8 ns t enzl enable pad z to low 7.1 9.4 ns t enhz enable pad high to z 11.5 15.3 ns t enlz enable pad low to z 11.5 15.3 ns t glh g to pad high 11.5 15.3 ns t ghl g to pad low 12.4 16.6 ns t lsu i/o latch output setup 0.4 0.5 ns t lh i/o latch output hold 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 11.5 15.4 ns t aco array latch clock-out (pad-to-pad) 32 i/o 16.3 21.7 ns d tlh capacitive loading, low to high 0.04 0.06 ns/pf d thl capacitive loading, high to low 0.06 0.08 ns/pf t wdo hard-wired wide decode output 0.05 0.07 ns cmos output module timing 1 t dlh data to pad high 6.3 8.3 ns t dhl data to pad low 5.1 6.8 ns t enzh enable pad z to high 6.6 8.8 ns t enzl enable pad z to low 7.1 9.4 ns t enhz enable pad high to z 11.5 15.3 ns t enlz enable pad low to z 11.5 15.3 ns t glh g to pad high 11.5 15.3 ns t ghl g to pad low 12.4 16.6 ns t lsu i/o latch setup 0.4 0.5 ns t lh i/o latch hold 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 13.7 18.2 ns t aco array latch clock-out (pad-to-pad) 32 i/o 19.2 25.6 ns d tlh capacitive loading, low to high 0.06 0.08 ns/pf d thl capacitive loading, high to low 0.05 0.07 ns/pf t wdo hard-wired wide decode output 0.05 0.07 ns notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
52 a32200dx timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module combinatorial functions t pd internal array module delay 2.8 3.8 ns t pdd internal decode module delay 3.4 4.6 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.6 2.1 ns t rd2 fo=2 routing delay 2.3 3.1 ns t rd3 fo=3 routing delay 2.9 3.9 ns t rd4 fo=4 routing delay 3.5 4.7 ns t rd5 fo=8 routing delay 6.2 8.2 ns t rdd decode-to-output routing delay 0.8 1.1 ns logic module sequential timing characteristics t co flip-flop clock-to-output 3.2 4.2 ns t go latch gate-to-output 2.8 3.8 ns t su flip-flop (latch) setup time 0.5 0.6 ns t h flip-flop (latch) hold time 0.0 0.0 ns t ro flip-flop (latch) reset to output 3.2 4.2 ns t suena flip-flop (latch) enable setup 0.9 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.3 5.8 ns t wasyn flip-flop (latch) asynchronous pulse width 5.7 7.6 ns note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
53 hirel fpgas a32200dx timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units synchronous sram operations t rc read cycle time 8.8 11.8 ns t wc write cycle time 8.8 11.8 ns t rckhl clock high/low time 4.4 5.9 ns t rco data valid after clock high/low 4.4 5.9 ns t adsu address/data setup time 2.1 2.8 ns t adh address/data hold time 0.0 0.0 ns t rensu read enable setup 0.8 1.1 ns t renh read enable hold 4.4 5.9 ns t wensu write enable setup 3.5 4.7 ns t wenh write enable hold 0.0 0.0 ns t bens block enable setup 3.6 4.8 ns t benh block enable hold 0.0 0.0 ns asynchronous sram operations t rpd asynchronous access time 10.6 14.1 ns t rdadv read address valid 11.5 15.3 ns t adsu address/data setup time 2.1 2.8 ns t adh address/data hold time 0.0 0.0 ns t rensua read enable setup to address valid 0.8 1.1 ns t renha read enable hold 4.4 5.9 ns t wensu write enable setup 3.5 4.7 ns t wenh write enable hold 0.0 0.0 ns t doh data out hold time 1.6 2.1 ns
54 a32200dx timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units input module propagation delays t inpy input data pad to y 1.9 2.6 ns t ingo input latch gate-to-output 4.6 6.0 ns t inh input latch hold 0.0 0.0 ns t insu input latch setup 0.7 0.9 ns t ila latch active pulse width 6.1 8.1 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 2.6 3.5 ns t ird2 fo=2 routing delay 3.4 4.6 ns t ird3 fo=3 routing delay 4.6 6.1 ns t ird4 fo=4 routing delay 5.4 7.2 ns t ird5 fo=8 routing delay 7.0 9.3 ns global clock network t ckh input low to high fo=32 fo=635 7.3 8.5 9.8 11.3 ns ns t ckl input high to low fo=32 fo=635 7.2 9.3 9.6 12.5 ns ns t pwh minimum pulse width high fo=32 fo=635 3.2 3.9 4.3 5.2 ns ns t pwl minimum pulse width low fo=32 fo=635 3.2 3.9 4.3 5.2 ns ns t cksw maximum skew fo=32 fo=635 1.8 1.8 2.4 2.4 ns ns t suext input latch external setup fo=32 fo=635 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 3.0 3.8 4.0 5.1 ns ns t p minimum period (1/fmax) fo=32 fo=635 5.8 6.8 7.7 9.1 ns ns f hmax maximum datapath frequency fo=32 fo=635 172 147 130 110 mhz mhz note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. optimization techniques may further reduc e delays by 0 to 4 ns.
55 hirel fpgas a32200dx timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units ttl output module timing 1 t dlh data to pad high 5.1 6.8 ns t dhl data to pad low 6.3 8.3 ns t enzh enable pad z to high 6.6 8.8 ns t enzl enable pad z to low 7.1 9.5 ns t enhz enable pad high to z 11.5 15.3 ns t enlz enable pad low to z 11.5 15.3 ns t glh g to pad high 11.5 15.3 ns t ghl g to pad low 12.3 16.5 ns t lsu i/o latch output setup 0.4 0.5 ns t lh i/o latch output hold 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 11.5 15.4 ns t aco array latch clock-out (pad-to-pad) 32 i/o 16.3 21.7 ns d tlh capacitive loading, low to high 0.04 0.06 ns/pf d thl capacitive loading, high to low 0.06 0.08 ns/pf t wdo hard-wired wide decode output 0.05 0.07 ns cmos output module timing 1 t dlh data to pad high 5.1 6.8 ns t dhl data to pad low 6.3 8.3 ns t enzh enable pad z to high 6.6 8.8 ns t enzl enable pad z to low 7.1 9.5 ns t enhz enable pad high to z 11.5 15.3 ns t enlz enable pad low to z 11.5 15.3 ns t glh g to pad high 11.5 15.3 ns t ghl g to pad low 12.3 16.5 ns t lsu i/o latch setup 0.4 0.5 ns t lh i/o latch hold 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 13.7 18.2 ns t aco array latch clock-out (pad-to-pad) 32 i/o 19.2 25.6 ns d tlh capacitive loading, low to high 0.06 0.08 ns/pf d thl capacitive loading, high to low 0.05 0.07 ns/pf t wdo hard-wired wide decode output 0.05 0.07 ns notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes .
56 pin description clk clock (input) act 1 only. ttl clock input for global clock distribution network. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clka clock a (input) act 2, 1200xl, 3200dx, and act 3 only. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clkb clock b (input) act 2, 1200xl, 3200dx, and act 3 only. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground low supply voltage. hclk dedicated (hard-wired) array clock (input) act 3 only. ttl clock input for sequential modules. this input is directly wired to each s-module and offers clock speeds independent of the number of s-modules being driven. this pin can also be used as an i/o. i/o input/output (input, output) i/o pin functions as an input, output, tristate, or bi-directional buffer. input and output levels are compatible with standard ttl and cmos specifications. in the act 3 and 3200dx families, unused i/os are automatically tri-stated. with this configuration, the input buffer internal to the i/o module is disabled. in the act 1, act 2 and 1200xl families, unused i/os are automatically configured as bi-directional buffers where each buffer is configured as a low driver. ioclk dedicated (hard-wired) i/o clock (input) act 3 only. ttl clock input for i/o modules. this input is directly wired to each i/o module and offers clock speeds independent of the number of i/o modules being driven. this pin can also be used as an i/o. iopcl dedicated (hard-wired) i/o preset/clear (input) act 3 only. ttl input for i/o preset or clear. this global input is directly wired to the preset and clear inputs of all i/o registers. this pin functions as an i/o when no i/o preset or clear macros are used. mode mode (input) the mode pin controls the use of diagnostic pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are active. when the mode pin is low, the pins function as i/os. to provide debugging capability, the mode pin should be terminated to gnd through a 10 k w resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra, i/o probe a (output) the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. the pins probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb, i/o probe b (output) the probe b pin is used to output data from any user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when verification has been completed. the pins probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. v cc 5.0v supply voltage high supply voltage. qclka/b,c,d quadrant clock (input/output) 3200dx only. these four pins are the quadrant clock inputs. when not used as a register control signal, these pins can function as general purpose i/o. tck test clock clock signal to shift the jtag data into the device. this pin functions as an i/o when the jtag fuse is not programmed. jtag pins are only available in the 3200dx device.
57 hirel fpgas tdi test data in serial data input for jtag instructions and data. data is shifted in on the rising edge of tclk. this pin functions as an i/o when the jtag fuse is not programmed. jtag pins are only available in the 3200dx device. tdo test data out serial data output for jtag instructions and test data. this pin functions as an i/o when the jtag fuse is not programmed. jtag pins are only available in the 3200dx device. tms test mode select serial data input for jtag test mode. data is shifted in on the rising edge of tclk. this pin functions as an i/o when the jtag fuse is not programmed. jtag pins are only available in the 3200dx device.
58 package pin assignments 84-pin cpga (top view) orientation pin (c3) a b c d e f g h j k l 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 84-pin cpga a b c d e f g h j k l
59 hirel fpgas 84-pin cpga pin number a1010b function a1020b function pin number a1010b function a1020b function a1 i/o i/o f9 clk, i/o clk, i/o a2 i/o i/o f10 gnd gnd a3 i/o i/o f11 i/o i/o a4 i/o i/o g1 i/o i/o a5 i/o i/o g2 v cc v cc a6 i/o i/o g3 i/o i/o a7 i/o i/o g9 i/o i/o a8 i/o i/o g10 gnd gnd a9 i/o i/o g11 i/o i/o a10 i/o i/o h1 i/o i/o a11 pra, i/o pra, i/o h2 i/o i/o b1 nc i/o h10 i/o i/o b2 nc nc h11 i/o i/o b3 i/o i/o j1 i/o i/o b4 i/o i/o j2 nc i/o b5 v cc v cc j5 i/o i/o b6 i/o i/o j6 i/o i/o b7 gnd gnd j7 i/o i/o b8 i/o i/o j10 nc i/o b9 i/o i/o j11 i/o i/o b10 prb, i/o prb, i/o k1 nc i/o b11 sdi, i/o sdi, i/o k2 v cc v cc c1 nc i/o k3 i/o i/o c2 nc i/o k4 i/o i/o c5 i/o i/o k5 gnd gnd c6 i/o i/o k6 i/o i/o c7 i/o i/o k7 v cc v cc c10 dclk, i/o dclk, i/o k8 i/o i/o c11 nc i/o k9 i/o i/o d1 i/o i/o k10 nc i/o d2 i/o i/o k11 nc i/o d10 nc i/o l1 nc i/o d11 nc i/o l2 i/o i/o e1 i/o i/o l3 i/o i/o e2 gnd gnd l4 i/o i/o e3 gnd gnd l5 i/o i/o e9 v cc v cc l6 i/o i/o e10 v cc v cc l7 i/o i/o e11 mode mode l8 i/o i/o f1 v cc v cc l9 i/o i/o f2 i/o i/o l10 i/o i/o f3 i/o i/o l11 i/o i/o
60 package pin assignments (continued) 132-pin cpga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 a b c d e f g h j k l m n a b c d e f g h j k l m n orientation pin 132-pin cpga
61 hirel fpgas 132-pin cpga pin number a1240a function pin number a1240a function pin number a1240a function a1 mode d8 i/o k7 v cc a2 i/o d11 i/o k8 i/o a3 i/o d12 i/o k11 i/o a4 i/o d13 i/o k12 gnd a5 i/o e1 i/o k13 i/o a6 i/o e2 i/o l1 i/o a7 i/o e3 gnd l2 i/o a8 i/o e11 gnd l3 i/o a9 i/o e12 gnd l4 i/o a10 i/o e13 i/o l5 gnd a11 i/o f1 i/o l6 i/o a12 i/o f2 i/o l7 v cc a13 i/o f3 i/o l8 i/o b1 i/o f4 gnd l9 gnd b2 i/o f10 i/o l10 i/o b3 i/o f11 i/o l11 i/o b4 i/o f12 i/o l12 i/o b5 gnd f13 i/o l13 i/o b6 clkb, i/o g1 i/o m1 i/o b7 clka, i/o g2 v cc m2 i/o b8 pra, i/o g3 v cc m3 i/o b9 gnd g4 v cc m4 i/o b10 i/o g10 v cc m5 i/o b11 i/o g11 v cc m6 i/o b12 sdi, i/o g12 v cc m7 i/o b13 i/o g13 v cc m8 i/o c1 i/o h1 i/o m9 gnd c2 i/o h2 i/o m10 i/o c3 dclk, i/o h3 i/o m11 i/o c4 i/o h4 i/o m12 i/o c5 gnd h10 i/o m13 i/o c6 prb, i/o h11 i/o n1 i/o c7 v cc h12 i/o n2 i/o c8 i/o h13 gnd n3 i/o c9 gnd j1 i/o n4 i/o c10 i/o j2 gnd n5 i/o c11 i/o j3 gnd n6 i/o c12 i/o j11 gnd n7 i/o c13 i/o j12 i/o n8 i/o d1 i/o j13 i/o n9 i/o d2 i/o k1 i/o n10 i/o d3 i/o k2 i/o n11 i/o d6 i/o k3 i/o n12 i/o d7 v cc k6 i/o n13 i/o
62 package pin assignments (continued) 133-pin cpga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 a b c d e f g h j k l m n 133-pin cpga a b c d e f g h j k l m n 1 2 3 4 5 6 7 8 9 10 11 12 13 orientation pin
63 hirel fpgas 133-pin cpga pin number a1425a function pin number a1425a function pin number a1425a function a1 nc d8 i/o k8 i/o a2 gnd d11 i/o k11 i/o a3 i/o d12 i/o k12 i/o a4 i/o d13 i/o k13 i/o a5 i/o e1 i/o l1 i/o a6 pra, i/o e2 i/o l2 i/o a7 nc e3 mode l3 gnd a8 i/o e11 v cc l4 i/o a9 i/o e12 i/o l5 i/o a10 i/o e13 i/o l6 prb, i/o a11 i/o f1 i/o l7 gnd a12 i/o f2 i/o l8 i/o a13 nc f3 i/o l9 i/o b1 i/o f4 i/o l10 iopcl, i/o b2 v cc f10 gnd l11 gnd b3 i/o f11 i/o l12 i/o b4 i/o f12 i/o l13 i/o b5 i/o f13 i/o m1 i/o b6 clkb, i/o g1 nc m2 v cc b7 v cc g2 v cc m3 gnd b8 i/o g3 gnd m4 i/o b9 i/o g4 i/o m5 i/o b10 i/o g10 i/o m6 i/o b11 i/o g11 gnd m7 v cc b12 v cc g12 v cc m8 i/o b13 i/o g13 nc m9 i/o c1 i/o h1 i/o m10 i/o c2 sdi, i/o h2 i/o m11 i/o c3 gnd h3 i/o m12 v cc c4 i/o h4 i/o m13 i/o c5 i/o h10 i/o n1 nc c6 i/o h11 i/o n2 i/o c7 gnd h12 i/o n3 i/o c8 i/o h13 i/o n4 i/o c9 i/o j1 i/o n5 i/o c10 ioclk, i/o j2 v cc n6 i/o c11 gnd j3 i/o n7 nc c12 gnd j11 i/o n8 i/o c13 i/o j12 v cc n9 i/o d1 i/o j13 i/o n10 i/o d2 i/o k1 i/o n11 i/o d3 i/o k2 i/o n12 gnd d4 dclk, i/o k3 i/o n13 nc d6 clka, i/o k6 i/o d7 i/o k7 hclka, i/o
64 package pin assignments (continued) 176-pin cpga (top view) . 1 a 234567891011 b c d e f g h j k l 176-pin cpga 1234567891011 12 12 13 13 14 14 15 15 m n p r a b c d e f g h j k l m n p r
65 hirel fpgas 176-pin cpga pin number a1280a function a1280xl function pin number a1280a function a1280xl function a1 i/o i/o c15 i/o i/o a2 i/o i/o d1 i/o i/o a3 i/o i/o d2 i/o i/o a4 i/o i/o d3 i/o i/o a5 i/o i/o d4 gnd gnd a6 i/o i/o d5 v cc v cc a7 i/o i/o d6 gnd gnd a8 i/o i/o d7 prb, i/o prb, i/o a9 clka, i/o clka, i/o d8 v cc v cc a10 i/o i/o d9 i/o i/o a11 i/o i/o d10 gnd gnd a12 i/o i/o d11 v cc v cc a13 i/o i/o d12 gnd gnd a14 i/o i/o d13 i/o i/o a15 i/o i/o d14 i/o i/o b1 i/o i/o d15 i/o i/o b2 i/o i/o e1 i/o i/o b3 dclk, i/o dclk, i/o e2 i/o i/o b4 i/o i/o e3 i/o i/o b5 i/o i/o e4 gnd gnd b6 i/o i/o e12 gnd gnd b7 i/o i/o e13 i/o i/o b8 clkb, i/o clkb, i/o e14 i/o i/o b9 i/o i/o e15 i/o i/o b10 i/o i/o f1 i/o i/o b11 i/o i/o f2 i/o i/o b12 i/o i/o f3 i/o i/o b13 i/o i/o f4 v cc v cc b14 sdi, i/o sdi, i/o f12 gnd gnd b15 i/o i/o f13 i/o i/o c1 i/o i/o f14 i/o i/o c2 i/o i/o f15 i/o i/o c3 mode mode g1 i/o i/o c4 i/o i/o g2 i/o i/o c5 i/o i/o g3 i/o i/o c6 i/o i/o g4 gnd gnd c7 i/o i/o g12 v cc v cc c8 gnd gnd g13 i/o i/o c9 pra, i/o pra, i/o g14 i/o i/o c10 i/o i/o g15 i/o i/o c11 i/o i/o h1 i/o i/o c12 i/o i/o h2 v cc v cc c13 i/o i/o h3 v cc v cc c14 i/o i/o h4 gnd gnd
66 h12 gnd gnd n2 i/o i/o h13 v cc v cc n3 i/o i/o h14 v cc v cc n4 i/o i/o h15 i/o i/o n5 i/o i/o j1 i/o i/o n6 i/o i/o j2 i/o i/o n7 i/o i/o j3 i/o i/o n8 v cc v cc j4 v cc v cc n9 i/o i/o j12 gnd gnd n10 i/o i/o j13 gnd gnd n11 i/o i/o j14 v cc v cc n12 i/o i/o j15 i/o i/o n13 i/o i/o k1 i/o i/o n14 i/o i/o k2 i/o i/o n15 i/o i/o k3 i/o i/o p1 i/o i/o k4 gnd gnd p2 i/o i/o k12 gnd gnd p3 i/o i/o k13 i/o i/o p4 i/o i/o k14 i/o i/o p5 i/o i/o k15 i/o i/o p6 i/o i/o l1 i/o i/o p7 i/o i/o l2 i/o i/o p8 i/o i/o l3 i/o i/o p9 i/o i/o l4 gnd gnd p10 i/o i/o l12 i/o i/o p11 i/o i/o l13 i/o i/o p12 i/o i/o l14 i/o i/o p13 i/o i/o l15 i/o i/o p14 i/o i/o m1 i/o i/o p15 i/o i/o m2 i/o i/o r1 i/o i/o m3 i/o i/o r2 i/o i/o m4 gnd gnd r3 i/o i/o m5 v cc v cc r4 i/o i/o m6 gnd gnd r5 i/o i/o m7 i/o i/o r6 i/o i/o m8 gnd gnd r7 i/o i/o m9 i/o i/o r8 i/o i/o m10 gnd gnd r9 i/o i/o m11 v cc v cc r10 i/o i/o m12 gnd gnd r11 i/o i/o m13 i/o i/o r12 i/o i/o m14 i/o i/o r13 i/o i/o m15 i/o i/o r14 i/o i/o n1 i/o i/o r15 i/o i/o 176-pin cpga (continued) pin number a1280a function a1280xl function pin number a1280a function a1280xl function
67 hirel fpgas package pin assignments (continued) 207-pin cpga (top view) 1 a b c d e f g h j k l m n p r s t 234567891011121314151617 1234567891011121314151617 a b c d e f g h j k l m n p r s t 207-pin cpga
68 207-pin cpga pin number a1460a function pin number a1460a function pin number a1460a function a1 nc c10 i/o g3 i/o a2 nc c11 i/o g4 i/o a3 i/o c12 i/o g14 i/o a4 i/o c13 i/o g15 i/o a5 i/o c14 i/o g16 i/o a6 i/o c15 gnd g17 i/o a7 i/o c16 i/o h1 pra, i/o a8 i/o c17 i/o h2 i/o a9 i/o d1 i/o h3 i/o a10 i/o d2 i/o h4 i/o a11 i/o d3 i/o h14 i/o a12 i/o d4 gnd h15 i/o a13 i/o d5 gnd h16 i/o a14 i/o d6 i/o h17 i/o a15 i/o d7 mode j1 i/o a16 nc d8 i/o j2 v cc a17 nc d9 gnd j3 clkb, i/o b1 nc d10 i/o j4 gnd b2 v cc d11 v cc j14 gnd b3 i/o d12 i/o j15 hclk, i/o b4 i/o d13 i/o j16 v cc b5 i/o d14 gnd j17 i/o b6 i/o d15 i/o k1 clka, i/o b7 i/o d16 i/o k2 i/o b8 i/o d17 i/o k3 i/o b9 v cc e1 i/o k4 i/o b10 i/o e2 i/o k14 i/o b11 i/o e3 i/o . k15 i/o b12 i/o e4 dclk, i/o k16 prb, i/o b13 i/o e14 i/o k17 i/o b14 i/o e15 i/o l1 i/o b15 i/o e16 i/o l2 i/o b16 v cc e17 i/o l3 i/o b17 nc f1 i/o l4 i/o c1 nc f2 i/o l14 i/o c2 nc f3 i/o l15 i/o c3 sdi, i/o f4 i/o l16 i/o c4 i/o f14 i/o l17 i/o c5 i/o f15 i/o m1 i/o c6 i/o f16 i/o m2 i/o c7 i/o f17 i/o m3 i/o c8 i/o g1 i/o m4 i/o c9 i/o g2 i/o m14 i/o
69 hirel fpgas m15 i/o p17 i/o s10 i/o m16 i/o r1 i/o s11 i/o m17 i/o r2 i/o s12 i/o n1 i/o r3 i/o s13 i/o n2 i/o r4 i/o s14 i/o n3 i/o r5 i/o s15 i/o n4 i/o r6 i/o s16 v cc n14 iopcl, i/o r7 i/o s17 nc n15 i/o r8 i/o t1 nc n16 i/o r9 i/o t2 nc n17 i/o r10 i/o t3 i/o p1 i/o r11 i/o t4 i/o p2 i/o r12 i/o t5 v cc p3 gnd r13 i/o t6 i/o p4 gnd r14 i/o t7 i/o p5 ioclk, i/o r15 gnd t8 i/o p6 i/o r16 i/o t9 i/o p7 gnd r17 i/o t10 i/o p8 i/o s1 nc t11 i/o p9 gnd s2 v cc t12 i/o p10 i/o s3 nc t13 i/o p11 i/o s4 i/o t14 i/o p12 v cc s5 i/o t15 i/o p13 i/o s6 i/o t16 nc p14 gnd s7 i/o t17 nc p15 i/o s8 i/o p16 i/o s9 v cc 207-pin cpga (continued) pin number a1460a function pin number a1460a function pin number a1460a function
70 package pin assignments (continued) 257-pin cpga (top view) a b c d e f g h j k l m n p r t v x y a b c d e f g h j k l m n p r t v x y 1 2 3 4 5 6 7 8 9 10 1112 13141516 1718 19 1 2 3 4 5 6 7 8 9 10 1112 13141516 1718 19 257-pin cpga
71 hirel fpgas 257-pin cpga pin number a14100a function pin number a14100a function pin number a14100a function a1 i/o c7 i/o e19 i/o a2 i/o c8 i/o f1 i/o a3 i/o c9 i/o f2 i/o a4 i/o c10 v cc f3 i/o a5 mode c11 i/o f4 i/o a6 i/o c12 i/o f16 i/o a7 i/o c13 v cc f17 i/o a8 i/o c14 i/o f18 i/o a9 i/o c15 i/o f19 i/o a10 i/o c16 i/o g1 i/o a11 i/o c17 v cc g2 i/o a12 i/o c18 i/o g3 i/o a13 i/o c19 i/o g4 i/o a14 i/o d1 i/o g5 i/o a15 i/o d2 i/o g15 i/o a16 i/o d3 i/o g16 i/o a17 i/o d4 gnd g17 i/o a18 i/o d5 i/o g18 i/o a19 i/o d6 i/o g19 i/o b1 i/o d7 i/o h1 i/o b2 i/o d8 i/o h2 i/o b3 i/o d9 i/o h3 i/o b4 sdi, i/o d10 gnd h4 i/o b5 i/o d11 i/o h16 i/o b6 i/o d12 i/o h17 i/o b7 i/o d13 i/o h18 i/o b8 i/o d14 i/o h19 i/o b9 i/o d15 i/o j1 pra, i/o b10 i/o d16 gnd j2 i/o b11 i/o d17 i/o j3 i/o b12 i/o d18 i/o j4 i/o b13 i/o d19 i/o j5 gnd b14 i/o e1 i/o j15 i/o b15 i/o e2 i/o j16 hclk, i/o b16 gnd e3 i/o j17 prb, i/o b17 i/o e4 dclk, i/o j18 i/o b18 i/o e5 nc j19 i/o b19 i/o e7 i/o k1 i/o c1 i/o e9 i/o k2 i/o c2 i/o e11 gnd k3 v cc c3 v cc e13 i/o k4 gnd c4 gnd e16 i/o k16 gnd c5 i/o e17 i/o k17 v cc c6 i/o e18 i/o k18 i/o
72 k19 i/o r9 i/o v17 v cc l1 i/o r11 i/o v18 i/o l2 i/o r13 i/o v19 i/o l3 i/o r16 iopcl, i/o x1 i/o l4 clka, i/o r17 i/o x2 i/o l5 clkb, i/o r18 i/o x3 i/o l15 gnd r19 i/o x4 i/o l16 i/o t1 i/o x5 i/o l17 i/o t2 i/o x6 i/o l18 i/o t3 i/o x7 gnd l19 i/o t4 gnd x8 i/o m1 i/o t5 ioclk, i/o x9 i/o m2 i/o t6 i/o x10 i/o m3 i/o t7 i/o x11 i/o m4 i/o t8 i/o x12 i/o m16 i/o t9 i/o x13 i/o m17 i/o t10 gnd x14 v cc m18 i/o t11 i/o x15 i/o m19 i/o t12 i/o x16 i/o n1 i/o t13 i/o x17 i/o n2 i/o t14 i/o x18 i/o n3 i/o t15 i/o x19 i/o n4 i/o t16 gnd y1 i/o n5 i/o t17 gnd y2 i/o n15 i/o t18 i/o y3 i/o n16 i/o t19 i/o y4 i/o n17 i/o v1 i/o y5 i/o n18 i/o v2 i/o y6 i/o n19 i/o v3 v cc y7 i/o p1 i/o v4 i/o y8 i/o p2 i/o v5 i/o y9 i/o p3 i/o v6 i/o y10 i/o p4 i/o v7 v cc y11 i/o p16 i/o v8 i/o y12 i/o p17 i/o v9 i/o y13 i/o p18 i/o v10 v cc y14 i/o p19 i/o v11 i/o y15 i/o r1 i/o v12 i/o y16 i/o r2 i/o v13 i/o y17 i/o r3 i/o v14 i/o y18 i/o r4 gnd v15 i/o y19 i/o r7 i/o v16 i/o 257-pin cpga (continued) pin number a14100a function pin number a14100a function pin number a14100a function
73 hirel fpgas package pin assignments (continued) 84-pin cqfp (top view) pin #1 index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 84-pin cqfp
74 84-pin cqfp pin number a1020b function A32100DX function pin number a1020b function A32100DX function 1 nc gnd 43 i/o gnd 2 i/o mode 44 i/o i/o 3 i/o i/o 45 i/o i/o 4 i/o i/o 46 i/o i/o 5 i/o i/o 47 i/o i/o 6 i/o i/o 48 i/o i/o 7gndv cc 49 gnd i/o 8 gnd i/o 50 gnd gnd 9 i/o i/o 51 i/o tck, i/o 10 i/o gnd 52 i/o gnd 11 i/o v cc 53 clka, i/o v cc 12 i/o v cc 54 i/o v cc 13 i/o i/o 55 mode v cc 14 v cc i/o 56 v cc v cc 15 v cc i/o 57 v cc i/o 16 i/o i/o 58 i/o i/o 17 i/o gnd 59 i/o gnd 18 i/o i/o 60 i/o i/o 19 i/o i/o 61 sdi, i/o i/o 20 i/o i/o 62 dclk, i/o i/o 21 i/o i/o 63 pra, i/o gnd 22 v cc gnd 64 prb, i/o sdi, i/o 23 i/o i/o 65 i/o i/o (wd) 24 i/o i/o 66 i/o i/o (wd) 25 i/o i/o (wd) 67 i/o i/o (wd) 26 i/o i/o (wd) 68 i/o i/o (wd) 27 i/o i/o 69 i/o qclkd, i/o 28 i/o qclka, i/o 70 i/o i/o (wd) 29 gnd gnd 71 gnd i/o (wd) 30 i/o i/o (wd) 72 i/o pra, i/o 31 i/o i/o 73 i/o clka, i/o 32 i/o gnd 74 i/o v cc 33 i/o v cc 75 i/o gnd 34 i/o i/o (wd) 76 i/o clkb, i/o 35 v cc i/o (wd) 77 v cc prb, i/o 36 i/o qclkb, i/o 78 i/o i/o (wd) 37 i/o i/o (wd) 79 i/o i/o (wd) 38 i/o gnd 80 i/o qclkc, i/o 39 i/o i/o (wd) 81 i/o gnd 40 i/o i/o (wd) 82 i/o i/o (wd) 41 i/o i/o (wd) 83 i/o i/o (wd) 42 i/o sdo, i/o 84 i/o dclk, i/o
75 hirel fpgas package pin assignments (continued) 132-pin cqfp (top view) 132-pin cqfp pin #1 index 132 131 130 129 128 127 126 125 124 107 106 105 104 103 102 101 100 34 35 36 37 38 39 40 41 42 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 92 93 94 95 96 97 98 99 33 32 31 30 29 28 27 26 25 8 7 6 5 4 3 2 1
76 132-pin cqfp pin number a1425a function pin number a1425a function pin number a1425a function 1 nc 45 i/o 89 v cc 2 gnd 46 i/o 90 gnd 3 sdi, i/o 47 i/o 91 v cc 4 i/o 48 prb, i/o 92 gnd 5 i/o 49 i/o 93 i/o 6 i/o 50 hclk, i/o 94 i/o 7 i/o 51 i/o 95 i/o 8 i/o 52 i/o 96 i/o 9 mode 53 i/o 97 i/o 10 gnd 54 i/o 98 ioclk, i/o 11 v cc 55 i/o 99 nc 12 i/o 56 i/o 100 nc 13 i/o 57 i/o 101 gnd 14 i/o 58 gnd 102 i/o 15 i/o 59 v cc 103 i/o 16 i/o 60 i/o 104 i/o 17 i/o 61 i/o 105 i/o 18 i/o 62 i/o 106 gnd 19 i/o 63 i/o 107 v cc 20 i/o 64 iopcl, i/o 108 i/o 21 i/o 65 gnd 109 i/o 22 v cc 66 nc 110 i/o 23 i/o 67 nc 111 i/o 24 i/o 68 i/o 112 i/o 25 i/o 69 i/o 113 i/o 26 gnd 70 i/o 114 i/o 27 v cc 71 i/o 115 i/o 28 i/o 72 i/o 116 clka, i/o 29 i/o 73 i/o 117 clkb, i/o 30 i/o 74 gnd 118 pra, i/o 31 i/o 75 v cc 119 i/o 32 i/o 76 i/o 120 i/o 33 i/o 77 i/o 121 i/o 34 nc 78 v cc 122 gnd 35 i/o 79 i/o 123 v cc 36 gnd 80 i/o 124 i/o 37 i/o 81 i/o 125 i/o 38 i/o 82 i/o 126 i/o 39 i/o 83 i/o 127 i/o 40 i/o 84 i/o 128 i/o 41 i/o 85 i/o 129 i/o 42 gnd 86 i/o 130 i/o 43 v cc 87 i/o 131 dclk, i/o 44 i/o 88 i/o 132 nc
77 hirel fpgas package pin assignments (continued) 172-pin cqfp (top view) 172-pin cqfp pin #1 index 172 171 170 169 168 167 166 165 164 137 136 135 134 133 132 131 130 44 45 46 47 48 49 50 51 52 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 122 123 124 125 126 127 128 129 43 42 41 40 39 38 37 36 35 8 7 6 5 4 3 2 1
78 172-pin cqfp pin number a1280a function a1280xl function pin number a1280a function a1280xl function 1 mode mode 45 i/o i/o 2 i/o i/o 46 i/o i/o 3 i/o i/o 47 i/o i/o 4 i/o i/o 48 i/o i/o 5 i/o i/o 49 i/o i/o 6 i/o i/o 50 v cc v cc 7 gnd gnd 51 i/o i/o 8 i/o i/o 52 i/o i/o 9 i/o i/o 53 i/o i/o 10 i/o i/o 54 i/o i/o 11 i/o i/o 55 gnd gnd 12 v cc v cc 56 i/o i/o 13 i/o i/o 57 i/o i/o 14 i/o i/o 58 i/o i/o 15 i/o i/o 59 i/o i/o 16 i/o i/o 60 i/o i/o 17 gnd gnd 61 i/o i/o 18 i/o i/o 62 i/o i/o 19 i/o i/o 63 i/o i/o 20 i/o i/o 64 i/o i/o 21 i/o i/o 65 gnd gnd 22 gnd gnd 66 v cc v cc 23 v cc v cc 67 i/o i/o 24 v cc v cc 68 i/o i/o 25 i/o i/o 69 i/o i/o 26 i/o i/o 70 i/o i/o 27 v cc v cc 71 i/o i/o 28 i/o i/o 72 i/o i/o 29 i/o i/o 73 i/o i/o 30 i/o i/o 74 i/o i/o 31 i/o i/o 75 gnd gnd 32 gnd gnd 76 i/o i/o 33 i/o i/o 77 i/o i/o 34 i/o i/o 78 i/o i/o 35 i/o i/o 79 i/o i/o 36 i/o i/o 80 v cc v cc 37 gnd gnd 81 i/o i/o 38 i/o i/o 82 i/o i/o 39 i/o i/o 83 i/o i/o 40 i/o i/o 84 i/o i/o 41 i/o i/o 85 i/o i/o 42 i/o i/o 86 i/o i/o 43 i/o i/o 87 i/o i/o 44 i/o i/o 88 i/o i/o
79 hirel fpgas 89 i/o i/o 131 sdi, i/o sdi, i/o 90 i/o i/o 132 i/o i/o 91 i/o i/o 133 i/o i/o 92 i/o i/o 134 i/o i/o 93 i/o i/o 135 i/o i/o 94 i/o i/o 136 v cc v cc 95 i/o i/o 137 i/o i/o 96 i/o i/o 138 i/o i/o 97 i/o i/o 139 i/o i/o 98 gnd gnd 140 i/o i/o 99 i/o i/o 141 gnd gnd 100 i/o i/o 142 i/o i/o 101 i/o i/o 143 i/o i/o 102 i/o i/o 144 i/o i/o 103 gnd gnd 145 i/o i/o 104 i/o i/o 146 i/o i/o 105 i/o i/o 147 i/o i/o 106 gnd gnd 148 pra, i/o pra, i/o 107 v cc v cc 149 i/o i/o 108 gnd gnd 150 clka, i/o clka, i/o 109 v cc v cc 151 v cc v cc 110 v cc v cc 152 gnd gnd 111 i/o i/o 153 i/o i/o 112 i/o i/o 154 clkb, i/o clkb, i/o 113 v cc v cc 155 i/o i/o 114 i/o i/o 156 prb, i/o prb, i/o 115 i/o i/o 157 i/o i/o 116 i/o i/o 158 i/o i/o 117 i/o i/o 159 i/o i/o 118 gnd gnd 160 i/o i/o 119 i/o i/o 161 gnd gnd 120 i/o i/o 162 i/o i/o 121 i/o i/o 163 i/o i/o 122 i/o i/o 164 i/o i/o 123 gnd gnd 165 i/o i/o 124 i/o i/o 166 v cc v cc 125 i/o i/o 167 i/o i/o 126 i/o i/o 168 i/o i/o 127 i/o i/o 169 i/o i/o 128 i/o i/o 170 i/o i/o 129 i/o i/o 171 dclk, i/o dclk, i/o 130 i/o i/o 172 i/o i/o 172-pin cqfp (continued) pin number a1280a function a1280xl function pin number a1280a function a1280xl function
80 package pin assignments (continued) 196-pin cqfp (top view) 196-pin cqfp pin #1 index 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 50 51 52 53 54 55 56 57 58 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 140 141 142 143 144 145 146 147 49 48 47 46 45 44 43 42 41 8 7 6 5 4 3 2 1
81 hirel fpgas 196-pin cqfp pin number a1460a function pin number a1460a function pin number a1460a function 1 gnd 44 i/o 87 i/o 2 sdi, i/o 45 i/o 88 i/o 3 i/o 46 i/o 89 i/o 4 i/o 47 i/o 90 i/o 5 i/o 48 i/o 91 i/o 6 i/o 49 i/o 92 i/o 7 i/o 50 i/o 93 i/o 8 i/o 51 gnd 94 v cc 9 i/o 52 gnd 95 i/o 10 i/o 53 i/o 96 i/o 11 mode 54 i/o 97 i/o 12 v cc 55 i/o 98 gnd 13 gnd 56 i/o 99 i/o 14 i/o 57 i/o 100 iopcl, i/o 15 i/o 58 i/o 101 gnd 16 i/o 59 v cc 102 i/o 17 i/o 60 i/o 103 i/o 18 i/o 61 i/o 104 i/o 19 i/o 62 i/o 105 i/o 20 i/o 63 i/o 106 i/o 21 i/o 64 gnd 107 i/o 22 i/o 65 i/o 108 i/o 23 i/o 66 i/o 109 i/o 24 i/o 67 i/o 110 v cc 25 i/o 68 i/o 111 v cc 26 i/o 69 i/o 112 gnd 27 i/o 70 i/o 113 i/o 28 i/o 71 i/o 114 i/o 29 i/o 72 i/o 115 i/o 30 i/o 73 i/o 116 i/o 31 i/o 74 i/o 117 i/o 32 i/o 75 prb, i/o 118 i/o 33 i/o 76 i/o 119 i/o 34 i/o 77 hclk, i/o 120 i/o 35 i/o 78 i/o 121 i/o 36 i/o 79 i/o 122 i/o 37 gnd 80 i/o 123 i/o 38 v cc 81 i/o 124 i/o 39 v cc 82 i/o 125 i/o 40 i/o 83 i/o 126 i/o 41 i/o 84 i/o 127 i/o 42 i/o 85 i/o 128 i/o 43 i/o 86 gnd 129 i/o
82 130 i/o 153 i/o 176 i/o 131 i/o 154 i/o 177 i/o 132 i/o 155 v cc 178 i/o 133 i/o 156 i/o 179 i/o 134 i/o 157 i/o 180 i/o 135 i/o 158 i/o 181 i/o 136 i/o 159 i/o 182 i/o 137 v cc 160 i/o 183 gnd 138 gnd 161 i/o 184 i/o 139 gnd 162 gnd 185 i/o 140 v cc 163 i/o 186 i/o 141 i/o 164 i/o 187 i/o 142 i/o 165 i/o 188 i/o 143 i/o 166 i/o 189 v cc 144 i/o 167 i/o 190 i/o 145 i/o 168 i/o 191 i/o 146 i/o 169 i/o 192 i/o 147 i/o 170 i/o 193 gnd 148 ioclk, i/o 171 i/o 194 i/o 149 gnd 172 clka, i/o 195 i/o 150 i/o 173 clkb, i/o 196 dclk, i/o 151 i/o 174 pra, i/o 152 i/o 175 i/o 196-pin cqfp (continued) pin number a1460a function pin number a1460a function pin number a1460a function
83 hirel fpgas package pin assignments (continued) 208-pin cqfp (top view) 208-pin cqfp pin #1 index 208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157 53 54 55 56 57 58 59 60 61 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 149 150 151 152 153 154 155 156 52 51 50 49 48 47 46 45 44 8 7 6 5 4 3 2 1
84 208-pin cqfp pin number A32100DX function pin number A32100DX function pin number A32100DX function 1 gnd 44 i/o 87 i/o 2v cc 45 i/o 88 i/o 3 mode 46 i/o 89 i/o 4 i/o 47 i/o 90 i/o 5 i/o 48 i/o 91 qclkb, i/o 6 i/o 49 i/o 92 i/o 7 i/o 50 i/o 93 i/o (wd) 8 i/o 51 i/o 94 i/o (wd) 9 i/o 52 gnd 95 i/o 10 i/o 53 gnd 96 i/o 11 i/o 54 tms, i/o 97 i/o 12 i/o 55 tdi, i/o 98 v cc 13 i/o 56 i/o 99 i/o 14 i/o 57 i/o (wd) 100 i/o (wd) 15 i/o 58 i/o (wd) 101 i/o (wd) 16 i/o 59 i/o 102 i/o 17 v cc 60 v cc 103 sdo, i/o 18 i/o 61 i/o 104 i/o 19 i/o 62 i/o 105 gnd 20 i/o 63 i/o 106 v cc 21 i/o 64 i/o 107 i/o 22 gnd 65 qclka, i/o 108 i/o 23 i/o 66 i/o (wd) 109 i/o 24 i/o 67 i/o (wd) 110 i/o 25 i/o 68 i/o 111 i/o 26 i/o 69 i/o 112 i/o 27 gnd 70 i/o (wd) 113 i/o 28 v cc 71 i/o (wd) 114 i/o 29 v cc 72 i/o 115 i/o 30 i/o 73 i/o 116 i/o 31 i/o 74 i/o 117 i/o 32 v cc 75 i/o 118 i/o 33 i/o 76 i/o 119 i/o 34 i/o 77 i/o 120 i/o 35 i/o 78 gnd 121 i/o 36 i/o 79 v cc 122 i/o 37 i/o 80 v cc 123 i/o 38 i/o 81 i/o 124 i/o 39 i/o 82 i/o 125 i/o 40 i/o 83 i/o 126 gnd 41 i/o 84 i/o 127 i/o 42 i/o 85 i/o (wd) 128 tck, i/o 43 i/o 86 i/o (wd) 129 gnd
85 hirel fpgas 130 v cc 157 gnd 184 gnd 131 gnd 158 i/o 185 i/o 132 v cc 159 sdi, i/o 186 clkb, i/o 133 v cc 160 i/o 187 i/o 134 i/o 161 i/o (wd) 188 prb, i/o 135 i/o 162 i/o (wd) 189 i/o 136 v cc 163 i/o 190 i/o (wd) 137 i/o 164 v cc 191 i/o (wd) 138 i/o 165 i/o 192 i/o 139 i/o 166 i/o 193 i/o 140 i/o 167 i/o 194 i/o (wd) 141 i/o 168 i/o (wd) 195 i/o (wd) 142 i/o 169 i/o (wd) 196 qclkc, i/o 143 i/o 170 i/o 197 i/o 144 i/o 171 qclkd, i/o 198 i/o 145 i/o 172 i/o 199 i/o 146 i/o 173 i/o 200 i/o 147 i/o 174 i/o 201 i/o 148 i/o 175 i/o 202 v cc 149 i/o 176 i/o (wd) 203 i/o (wd) 150 gnd 177 i/o (wd) 204 i/o (wd) 151 i/o 178 pra, i/o 205 i/o 152 i/o 179 i/o 206 i/o 153 i/o 180 clka, i/o 207 dclk, i/o 154 i/o 181 i/o 208 i/o 155 i/o 182 v cc 156 i/o 183 v cc 208-pin cqfp (continued) pin number A32100DX function pin number A32100DX function pin number A32100DX function
86 package pin assignments (continued) 256-pin cqfp (top view) 256-pin cqfp pin #1 index 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 185 186 187 188 189 190 191 192 64 63 62 61 60 59 58 57 56 8 7 6 5 4 3 2 1
87 hirel fpgas 256-pin cqfp pin number a14100a function a32200dx function pin number a14100a function a32200dx function pin number a14100a function a32200dx function 1 gnd nc 45 i/o i/o 89 i/o i/o 2 sdi, i/o gnd 46 v cc i/o 90 prb, i/o i/o 3 i/o i/o 47 i/o i/o 91 gnd i/o 4 i/o i/o 48 i/o gnd 92 v cc i/o 5 i/o i/o 49 i/o i/o 93 gnd i/o 6 i/o i/o 50 i/o i/o 94 v cc i/o 7 i/o i/o 51 i/o i/o 95 i/o v cc 8 i/o i/o 52 i/o i/o 96 hclk, i/o v cc 9 i/o i/o 53 i/o i/o 97 i/o gnd 10 i/o gnd 54 i/o i/o 98 i/o gnd 11 mode i/o 55 i/o i/o 99 i/o i/o 12 i/o i/o 56 i/o i/o 100 i/o i/o 13 i/o i/o 57 i/o i/o 101 i/o i/o 14 i/o i/o 58 i/o i/o 102 i/o i/o 15 i/o i/o 59 gnd i/o 103 i/o i/o 16 i/o i/o 60 i/o v cc 104 i/o i/o 17 i/o i/o 61 i/o gnd 105 i/o i/o (wd) 18 i/o i/o 62 i/o gnd 106 i/o i/o (wd) 19 i/o i/o 63 i/o nc 107 i/o i/o 20 i/o i/o 64 i/o nc 108 i/o i/o 21 i/o i/o 65 i/o nc 109 i/o i/o (wd) 22 i/o i/o 66 i/o i/o 110 gnd i/o (wd) 23 i/o i/o 67 i/o sdo, i/o 111 i/o i/o 24 i/o i/o 68 i/o i/o 112 i/o qclka, i/o 25 i/o i/o 69 i/o i/o (wd) 113 i/o i/o 26 i/o v cc 70 i/o i/o (wd) 114 i/o gnd 27 i/o i/o 71 i/o i/o 115 i/o i/o 28 v cc i/o 72 i/o v cc 116 i/o i/o 29 gnd v cc 73 i/o i/o 117 i/o i/o 30 v cc v cc 74 i/o i/o 118 i/o i/o 31 gnd gnd 75 i/o i/o 119 i/o v cc 32 i/o v cc 76 i/o i/o (wd) 120 i/o i/o 33 i/o gnd 77 i/o gnd 121 i/o i/o (wd) 34 i/o tck, i/o 78 i/o i/o (wd) 122 i/o i/o (wd) 35 i/o i/o 79 i/o i/o 123 i/o i/o 36 i/o gnd 80 i/o qclkb, i/o 124 i/o i/o 37 i/o i/o 81 i/o i/o 125 i/o tdi, i/o 38 i/o i/o 82 i/o i/o 126 i/o tms, i/o 39 i/o i/o 83 i/o i/o 127 iopcl, i/o gnd 40 i/o i/o 84 i/o i/o 128 gnd nc 41 i/o i/o 85 i/o i/o 129 i/o nc 42 i/o i/o 86 i/o i/o 130 i/o nc 43 i/o i/o 87 i/o i/o (wd) 131 i/o gnd 44 i/o i/o 88 i/o i/o (wd) 132 i/o i/o
88 133 i/o i/o 175 gnd i/o 217 i/o i/o 134 i/o i/o 176 gnd i/o 218 i/o prb, i/o 135 i/o i/o 177 i/o i/o 219 clka, i/o i/o 136 i/o i/o 178 i/o i/o 220 clkb, i/o clkb, i/o 137 i/o i/o 179 i/o i/o 221 v cc i/o 138 i/o i/o 180 i/o gnd 222 gnd gnd 139 i/o gnd 181 i/o i/o 223 v cc gnd 140 i/o i/o 182 i/o i/o 224 gnd v cc 141 v cc i/o 183 i/o i/o 225 pra, i/o v cc 142 i/o i/o 184 i/o i/o 226 i/o i/o 143 i/o i/o 185 i/o i/o 227 i/o clka, i/o 144 i/o i/o 186 i/o i/o 228 i/o i/o 145 i/o i/o 187 i/o i/o 229 i/o pra, i/o 146 i/o i/o 188 ioclk, i/o mode 230 i/o i/o 147 i/o i/o 189 gnd v cc 231 i/o i/o 148 i/o i/o 190 i/o gnd 232 i/o i/o (wd) 149 i/o i/o 191 i/o nc 233 i/o i/o (wd) 150 i/o i/o 192 i/o nc 234 i/o i/o 151 i/o i/o 193 i/o nc 235 i/o i/o 152 i/o i/o 194 i/o i/o 236 i/o i/o 153 i/o i/o 195 i/o dclk, i/o 237 i/o i/o 154 i/o i/o 196 i/o i/o 238 i/o i/o 155 i/o v cc 197 i/o i/o 239 i/o i/o 156 i/o i/o 198 i/o i/o 240 gnd qclkd, i/o 157 i/o i/o 199 i/o i/o (wd) 241 i/o i/o 158 gnd v cc 200 i/o i/o (wd) 242 i/o i/o (wd) 159 v cc v cc 201 i/o v cc 243 i/o gnd 160 gnd gnd 202 i/o i/o 244 i/o i/o (wd) 161 v cc i/o 203 i/o i/o 245 i/o i/o 162 i/o i/o 204 i/o i/o 246 i/o i/o 163 i/o i/o 205 i/o i/o 247 i/o i/o 164 i/o i/o 206 i/o gnd 248 i/o v cc 165 i/o gnd 207 i/o i/o 249 i/o i/o 166 i/o i/o 208 i/o i/o 250 i/o i/o (wd) 167 i/o i/o 209 i/o qclkc, i/o 251 i/o i/o (wd) 168 i/o i/o 210 i/o i/o 252 i/o i/o 169 i/o i/o 211 i/o i/o (wd) 253 i/o sdi, i/o 170 i/o v cc 212 i/o i/o (wd) 254 i/o i/o 171 i/o i/o 213 i/o i/o 255 i/o gnd 172 i/o i/o 214 i/o i/o 256 dclk, i/o nc 173 i/o i/o 215 i/o i/o (wd) 174 v cc i/o 216 i/o i/o (wd) 256-pin cqfp (continued) pin number a14100a function a32200dx function pin number a14100a function a32200dx function pin number a14100a function a32200dx function
89 hirel fpgas package mechanical drawings 84-pin cpga notes: 1. all dimensions are in inches unless otherwise stated. 2. bscbasic spacing between centers. this is a theoretical true position dimension and so has no tolerance. orientation pin 1.100" .020" square .080" .110" .120" .140" .100" bsc 0.18" .002" .050" .010" 1.000 bsc .045 .055 l k j h g f e d c b a 11 10 9 8 7 6 5 4 3 2 1 pin #1 id
90 package mechanical drawings (continued) 132-pin cpga notes: 1. all dimensions are in inches unless otherwise stated. 2. bscbasic spacing between centers. this is a theoretical true position dimension and so has no tolerance. orientation pin 1.360" .015" square .120" .140" .100" bsc 0.18" .002" .050" .010" 1.200 bsc .085" .110" pin #1 id .045 .055 11 12 13 10 9 8 7 6 5 4 3 2 1 n m l k j h g f e d c b a
91 hirel fpgas package mechanical drawings (continued) 133-pin cpga notes: 1. all dimensions are in inches unless otherwise stated. 2. bscbasic spacing between centers. this is a theoretical true position dimension and so has no tolerance. 1.360" 0.015" square 0.120" 0.140" 0.100" bsc 0.018" 0.002" 0.050" 0.010" pin #1 1.200" bsc 0.100" 0.130" 0.045" 0.055" orientation pin 11 12 13 10 9 8 7 6 5 4 3 2 1 n m l k j h g f e d c b a top view bottom view side view
92 package mechanical drawings (continued) 176-pin cpga notes: 1. all dimensions are in inches unless otherwise stated. 2. bscbasic spacing between centers. this is a theoretical true position dimension and so has no tolerance. index mark 0.018" .002" 0.102" 0.132" 0.050" .005" 1.400 bsc 0.100" bsc 1.570" .015" square 0.120" 0.140" 11 12 13 14 15 10 9 8 7 6 5 4 3 2 1 r p n m l k j h g f e d c b a
93 hirel fpgas package mechanical drawings (continued) 207-pin cpga notes: 1. all dimensions are in inches unless otherwise stated. 2. bscbasic spacing between centers. this is a theoretical true position dimension and so has no tolerance. index mark 0.100" bsc 0.120" 0.015" 11 12 13 14 15 16 17 10 9 8 7 6 5 4 3 2 1 u t r p n m l k j h g f e d c b a 1.600" bsc 0.018" 0.002" 0.180" 0.010" 0.05" 0.005" 1.77" 0.010" square 0.05" 0.005" top view side view bottom view
94 package mechanical drawings (continued) 257-pin cpga notes: 1. all dimensions are in inches unless otherwise stated. 2. bscbasic spacing between centers. this is a theoretical true position dimension and so has no tolerance. 0.105" 0.012" 0.05" 0.005" 0.100" bsc y x v t r p n m l k j h g f e d c b a 1 2345678910111213141516171819 0.018" 0.002" 0.180" 0.010" 0.05" 0.01" 1.970" 0.015" square 1.800" bsc top view side view bottom view
95 hirel fpgas package mechanical drawings (continued) 84-pin cqfp notes: 1. seal ring and lid are connected to ground. 2. lead material is kovar with minimum 50 microinches gold plate over nickel. 3. packages are shipped unformed with the ceramic tie bar in a test carrier. d2 d1 e a1 a c h e2 e1 b l1 f lid top view side view
96 package mechanical drawings (continued) 132-pin, 172-pin, 196-pin, 208-pin, and 256-pin cqfp (cavity up) notes: 1. outside leadframe holes (from dimension h) are circular for the cq208 and cq256. 2. seal ring and lid are connected to ground. 3. lead material is kovar with minimum 50 microinches gold plate over nickel. 4. packages are shipped unformed with the ceramic tie bar. 5. 32200dx C cq208 has a heat sink on the back. a b h d1 d2 e2 e1 f l1 k ceramic tie bar no. 1 e a1 c lead kovar lid top view side view
97 hirel fpgas cqfp (ceramic quad flat pack) cqfp 84 cqfp 132 cqfp 172 cqfp 196 symbol min. nom. max. min. nom. max. min. nom. max. min. nom. max. a 0.070 0.090 0.100 0.094 0.105 0.116 0.094 0.105 0.116 0.094 0.105 0.116 a1 0.060 0.075 0.080 0.080 0.090 0.100 0.080 0.090 0.100 0.080 0.090 0.100 b 0.008 0.010 0.012 0.007 0.008 0.010 0.007 0.008 0.010 0.007 0.008 0.010 c 0.004 0.006 0.008 0.004 0.006 0.008 0.004 0.006 0.008 0.004 0.006 0.008 d1/e1 0.640 0.650 0.660 0.940 0.950 0.960 1.168 1.180 1.192 1.336 1.350 1.364 d2/e2 0.500 bsc 0.800 bsc 1.050 bsc 1.200 bsc e 0.025 bsc 0.025 bsc 0.025 bsc 0.025 bsc f 0.130 0.140 0.150 0.325 0.350 0.375 0.175 0.200 0.225 0.175 0.200 0.225 h 1.460 bsc 2.320 bsc 2.320 bsc 2.320 bsc k 2.140 bsc 2.140 bsc 2.140 bsc l1 1.595 1.600 1.615 2.485 2.500 2.505 2.485 2.495 2.505 2.485 2.495 2.505 note: 1. all dimensions are in inches except cq208 and cq256, which are in millimeters. 2. bsc equals basic spacing between centers. this is a theoretical true position dimension and so has no tolerance. cqfp (ceramic quad flat pack) cqfp 208 cqfp 256 symbol min. nom. max. min. nom. max. a 2.78 3.17 3.56 2.28 2.67 3.06 a1 2.43 2.79 3.15 1.93 2.29 2.65 b 0.18 0.20 0.22 0.18 0.20 0.22 c 0.11 0.15 0.17 0.11 0.15 0.18 d1/e1 28.96 29.21 29.46 35.64 36.00 36.36 d2/e2 25.5 bsc 31.5 bsc e 0.50 bsc 0.50 bsc f 7.05 7.75 8.45 7.05 7.75 8.45 h 70.00 bsc 70.00 bsc k 65.90 bsc 65.90 bsc l1 74.60 75.00 75.40 74.60 75.00 75.40 note: 1. all dimensions are in inches except cq208 and cq256, which are in millimeters. 2. bsc equals basic spacing between centers. this is a theoretical true position dimension and so has no tolerance.
actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. http://www.actel.com actel europe ltd. daneshill house, lutyens close basingstoke, hampshire rg24 8ag united kingdom tel: +44-(0)125-630-5600 fax: +44-(0)125-635-5420 actel corporation 955 east arques avenue sunnyvale, california 94086 usa tel: (408) 739-1010 fax: (408) 739-1540 actel asia-pacific exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan tel: +81-(0)3-3445-7671 fax: +81-(0)3-3445-7668 5192641-2/1.00

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